Patents by Inventor Yasuhiko Nara

Yasuhiko Nara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020109088
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 5, 2002
    Publication date: August 15, 2002
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Publication number: 20020105648
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 4, 2002
    Publication date: August 8, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Patent number: 6421122
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: July 16, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Publication number: 20020057831
    Abstract: A pattern inspection method in which an image can be detected without an image detection error due to an adverse effect to be given by such factors as ions implanted in a wafer, pattern connection/no-connection, and pattern edge formation. A digital image of an object substrate is attained through microscopic observation thereof, the attained digital image is examined to detect defects while masking a region pre-registered in terms of coordinates or while masking a pattern meeting a pre-registered pattern, and an image of each of the defects thus detected is displayed. Further, each of the defects detected using the digital image attained through microscopic observation is checked to judge whether its feature meets a pre-registered feature or not. Defects having a feature that meets the pre-registered feature are so displayed that they can be turned/off, or they are so displayed as to be distinguishable from the other defects.
    Type: Application
    Filed: November 9, 2001
    Publication date: May 16, 2002
    Inventors: Takashi Hiroi, Masahiro Watanabe, Chie Shishido, Aritoshi Sugimoto, Maki Tanaka, Hiroshi Miyai, Asahiro Kuni, Yasuhiko Nara
  • Patent number: 6388747
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: May 14, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi
  • Publication number: 20020054703
    Abstract: A pattern inspection method in which an image can be detected without an image detection error due to an adverse effect to be given by such factors as ions implanted in a wafer, pattern connection/no-connection, and pattern edge formation. A digital image of an object substrate is attained through microscopic observation thereof, the attained digital image is examined to detect defects while masking a region pre-registered in terms of coordinates or while masking a pattern meeting a pre-registered pattern, and an image of each of the defects thus detected is displayed. Further, each of the defects detected using the digital image attained through microscopic observation is checked to judge whether its feature meets a pre-registered feature or not. Defects having a feature that meets the pre-registered feature are so displayed that they can be turned/off, or they are so displayed as to be distinguishable from the other defects.
    Type: Application
    Filed: November 8, 2001
    Publication date: May 9, 2002
    Inventors: Takashi Hiroi, Masahiro Watanabe, Chie Shishido, Aritoshi Sugimoto, Maki Tanaka, Hiroshi Miyai, Asahiro Kuni, Yasuhiko Nara
  • Publication number: 20020051565
    Abstract: The present invention provides techniques, including a method and system, for inspecting for defects in a circuit pattern on a semi-conductor material. One specific embodiment provides a trial inspection threshold setup method, where the initial threshold is modified after a defect analysis of trial inspection stored data. The modified threshold is then used as the threshold in actual inspection.
    Type: Application
    Filed: March 8, 2001
    Publication date: May 2, 2002
    Inventors: Takashi Hiroi, Masahiro Watanabe, Chie Shishido, Asahiro Kuni, Maki Tanaka, Hiroshi Miyai, Yasuhiko Nara, Mari Nozoe
  • Publication number: 20010021020
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 11, 2001
    Publication date: September 13, 2001
    Inventors: Yasuhiko Nara, Takashi Hiori
  • Publication number: 20010021019
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 11, 2001
    Publication date: September 13, 2001
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi
  • Publication number: 20010019411
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 11, 2001
    Publication date: September 6, 2001
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Publication number: 20010015805
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 11, 2001
    Publication date: August 23, 2001
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi
  • Publication number: 20010011706
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 11, 2001
    Publication date: August 9, 2001
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito