Patents by Inventor Yasuhiko Takahashi

Yasuhiko Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8193146
    Abstract: The present invention relates to a method for improving symptom of mood disorder or its related disorder comprising a step of allowing Gm1 protein and the like to be excessively present in a brain of a mammal, and a non-human mammal, to which the method has been applied, and the like.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: June 5, 2012
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Yasuhiko Takahashi, Kenji Oeda
  • Publication number: 20110275207
    Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
    Type: Application
    Filed: July 5, 2011
    Publication date: November 10, 2011
    Inventors: Masahiro MONIWA, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
  • Publication number: 20110214003
    Abstract: Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock switching in a clock selector operable to switch between clock signals including a first clock signal based on first and second clock-stop-permission signals and a clock-resume-permission signal. The clock-control-signal-generation circuit includes: a before-switching clock processing unit; and an after-switching clock processing unit. In each of the before- and after-switching clock processing units, the high-frequency clock processing subunit and the low-frequency clock processing subunit take partial charges of processing of clock signals involved in the switching respectively, whereby the processing is speeded up.
    Type: Application
    Filed: February 25, 2011
    Publication date: September 1, 2011
    Inventors: Yoshikazu NARA, Yasuhiko Takahashi
  • Patent number: 7981738
    Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: July 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masahiro Moniwa, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
  • Publication number: 20110129848
    Abstract: A novel protein (Gm1) includes an amino acid sequence part having a high homology with a domain having a high homology with a GTP binding site and a GTPase site conserved among G protein ? subunits and a trimer forming domain conserved among G protein ? subunits. The Gm1 protein is involved in signal transduction via a G protein-coupled receptor (GPCR) stimulation. The Gm1 protein is expressed intensively in human brain, thymus, testes, spleen, small intestine, uterus and heart.
    Type: Application
    Filed: February 1, 2011
    Publication date: June 2, 2011
    Applicant: SUMITOMO CHEMICAL COMPANY, LTD.
    Inventors: Yasuhiko Takahashi, Yasuo Matsumoto, Kenji Oeda
  • Patent number: 7893203
    Abstract: A novel protein (Gm1) includes an amino acid sequence part having a high homology with a domain having a high homology with a GTP binding site and a GTPase site conserved among G protein ? subunits and a trimer forming domain conserved among G protein ? subunits. The Gm1 protein is involved in signal transduction via a G protein-coupled receptor (GPCR) stimulation. The Gm1 protein is expressed intensively in human brain, thymus, testes, spleen, small intestine, uterus and heart. A method for screening for a substance capable of regulating a cellular signal transduction employs a polynucleotide encoding the Gm1 protein.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: February 22, 2011
    Assignee: Sumitomo Chemical Company, Ltd.
    Inventors: Yasuhiko Takahashi, Yasuo Matsumoto, Kenji Oeda
  • Publication number: 20110034017
    Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
    Type: Application
    Filed: October 22, 2010
    Publication date: February 10, 2011
    Inventors: Masahiro MONIWA, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
  • Patent number: 7852584
    Abstract: A head IC adjusts an amplitude level of head read signals with regard to scattering in head output characteristics, so as to conform to the input dynamic range of the read channel AGC. An AGC amplifier is provided in a head IC connected to a read channel, and the feedback response speed of the AGC circuit of the head IC is set to be substantially slower than the feedback response speed of the AGC circuit of the read channel. Within the head IC, the amplitude of signals from the head is automatically adjusted, enabling adjustment of the input signal level to the input dynamic range of the AGC amplifier of the read channel. The AGC circuit of the head IC has no effect on the faster AGC operation of the AGC circuit of the read channel.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: December 14, 2010
    Assignee: Toshiba Storage Device Corporation
    Inventors: Jyunko Matsui, Yasuhiko Takahashi
  • Patent number: 7829952
    Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: November 9, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Masahiro Moniwa, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
  • Publication number: 20100068625
    Abstract: The present invention relates to a novel compound characterized by having a one-dimensional tunnel structure and being represented by the chemical formula H2Ti12O25, a method for manufacturing the same, and a lithium secondary battery containing, as a constituent thereof, an electrode produced by using the novel titanium oxide as an active material, and expected to demonstrate superior charge/discharge cycle characteristics over a long period of time as well as high capacity.
    Type: Application
    Filed: March 5, 2008
    Publication date: March 18, 2010
    Inventors: Junji AKIMOTO, Norihito KIJIMA, Hiroshi HAYAKAWA, Yasuhiko TAKAHASHI, Yasushi IDEMOTO
  • Publication number: 20090261390
    Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
    Type: Application
    Filed: June 25, 2009
    Publication date: October 22, 2009
    Inventors: Masahiro MONIWA, Hiraku CHAKIHARA, Kousuke OKUYAMA, Yasuhiko TAKAHASHI
  • Patent number: 7606003
    Abstract: A storage apparatus and a magnetic head driving device includes a recording/reproducing head including a write element and a magnetoresistive element, a driving circuit for driving the write element and the magnetoresistive element, and write wires and read wires which connect the recording/reproducing head to the driving circuit. The write wires and the read wires are disposed in parallel in at least a portion between the recording/reproducing head and the driving circuit. At a location between the recording/reproducing head and the driving circuit, either of the write wires and the read wires are disposed so that a polarity of the either of the write wires and the read wires is reversed with respect to a polarity of the other of the write wires and the read wires.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: October 20, 2009
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Amemiya, Tetsuyuki Kubota, Yasuhiko Takahashi
  • Patent number: 7598133
    Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly comprise laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: October 6, 2009
    Assignee: Renesas Technology Corp
    Inventors: Masahiro Moniwa, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
  • Publication number: 20090210949
    Abstract: The present invention relates to a method for improving symptom of mood disorder or its related disorder comprising a step of allowing Gm1 protein and the like to be excessively present in a brain of a mammal, and a non-human mammal, to which the method has been applied, and the like.
    Type: Application
    Filed: March 15, 2006
    Publication date: August 20, 2009
    Applicant: SUMITOMO CHEMICAL COMPANY LIMITED
    Inventors: Yasuhiko Takahashi, Kenji Oeda
  • Publication number: 20090042789
    Abstract: The present invention relates to a method for improving symptom of mood disorder or its related disorder comprising a step of allowing activated-type Gm1 protein and the like to be excessively present in a brain of a mammal, and a non-human mammal, to which the method has been applied, and the like.
    Type: Application
    Filed: May 17, 2006
    Publication date: February 12, 2009
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Yasuhiko Takahashi, Kenji Oeda
  • Patent number: 7460392
    Abstract: In a semiconductor memory device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is achieved. A voltage, which is set on the condition that the difference between a source potential applied to each of the first and second transistors and the potential of a select level of a word line becomes greater than or equal to a threshold voltage of each of the third and fourth transistors, is supplied to a source electrode of each of the first and second transistors, to thereby perform “0” write compensation.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: December 2, 2008
    Assignee: Renesas Technology Corporation
    Inventors: Yasuhiko Takahashi, Takayuki Tanaka
  • Publication number: 20080233126
    Abstract: A novel protein (Gm1) includes an amino acid sequence part having a high homology with a domain having a high homology with a GTP binding site and a GTPase site conserved among G protein ? subunits and a trimer forming domain conserved among G protein ? subunits. The Gm1 protein is involved in signal transduction via a G protein-coupled receptor (GPCR) stimulation. The Gm1 protein is expressed intensively in human brain, thymus, testes, spleen, small intestine, uterus and heart. A method for screening for a substance capable of regulating a cellular signal transduction employs a polynucleotide encoding the Gm1 protein.
    Type: Application
    Filed: May 9, 2008
    Publication date: September 25, 2008
    Applicant: SUMITOMO CHEMICAL COMPANY, LTD.
    Inventors: Yasuhiko Takahashi, Yasuo Matsumoto, Kenji Oeda
  • Patent number: 7371687
    Abstract: An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: May 13, 2008
    Assignee: Renesas Technology Corporation
    Inventors: Ryo Fujita, Osamu Kubo, Kouki Noguchi, Masaharu Kubo, Michihiro Mishima, Yasuhiko Takahashi
  • Patent number: 7371541
    Abstract: We identified a novel protein (Gm1) comprising an amino acid sequence part having a high homology with a domain having a high homology with a GTP binding site and a GTPase site conserved among G protein ? subunits and a trimer forming domain conserved among G protein ? subunits. The Gm1 is involved in an signal transduction via a G protein-coupled receptor (GPCR) stimulation. Accordingly, this protein is considered to be a novel G protein. The Gm1 is expressed intensively in human brain, thymus, testes, spleen, small intestine, uterus and heart. We also established a method for screening for a substance capable of regulating a cellular signal transduction employing a polynucleotide encoding the Gm1.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: May 13, 2008
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Yasuhiko Takahashi, Yasuo Matsumoto, Kenji Oeda
  • Publication number: 20080100944
    Abstract: A head IC adjusts an amplitude level of head read signals with regard to scattering in head output characteristics, so as to conform to the input dynamic range of the read channel AGC. An AGC amplifier is provided in a head IC connected to a read channel, and the feedback response speed of the AGC circuit of the head IC is set to be substantially slower than the feedback response speed of the AGC circuit of the read channel. Within the head IC, the amplitude of signals from the head is automatically adjusted, enabling adjustment of the input signal level to the input dynamic range of the AGC amplifier of the read channel. The AGC circuit of the head IC has no effect on the faster AGC operation of the AGC circuit of the read channel.
    Type: Application
    Filed: December 21, 2007
    Publication date: May 1, 2008
    Applicant: Fujitsu Limited
    Inventors: Jyunko Matsui, Yasuhiko Takahashi