Patents by Inventor Yasuhiro Sugaya

Yasuhiro Sugaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11949090
    Abstract: A winding-start region that is closer to a winding-start side than a positive electrode core exposed part has positive electrode mixture unit amounts of a positive electrode inner mixture layer and a positive electrode outer mixture layer that are approximately uniform or increasing toward a winding-end side in the winding direction. A winding-start facing region has negative electrode mixture unit amounts of a negative electrode inner mixture layer and a negative electrode outer mixture layer that are approximately uniform or increasing toward the winding-end side. The positive electrode inner mixture layer and the positive electrode outer mixture layer each have a positive electrode mixture unit amount that differs at two or more locations, excluding the positive electrode core exposed part. The negative electrode inner mixture layer and the negative electrode outer mixture each have a fluctuating part where the negative electrode mixture unit amount fluctuates toward the winding-end side.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: April 2, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hajime Nishino, Yasuhiro Sugaya, Takanori Maruo
  • Publication number: 20210050586
    Abstract: A winding-start region that is closer to a winding-start side than a positive electrode core exposed part has positive electrode mixture unit amounts of a positive electrode inner mixture layer and a positive electrode outer mixture layer that are approximately uniform or increasing toward a winding-end side in the winding direction. A winding-start facing region has negative electrode mixture unit amounts of a negative electrode inner mixture layer and a negative electrode outer mixture layer that are approximately uniform or increasing toward the winding-end side. The positive electrode inner mixture layer and the positive electrode outer mixture layer each have a positive electrode mixture unit amount that differs at two or more locations, excluding the positive electrode core exposed part. The negative electrode inner mixture layer and the negative electrode outer mixture each have a fluctuating part where the negative electrode mixture unit amount fluctuates toward the winding-end side.
    Type: Application
    Filed: February 26, 2019
    Publication date: February 18, 2021
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hajime Nishino, Yasuhiro Sugaya, Takanori Maruo
  • Publication number: 20190181495
    Abstract: A lithium ion secondary battery includes a positive electrode, a negative electrode, a separator disposed between the positive electrode and the negative electrode, and a nonaqueous electrolyte having permeated the positive electrode, the negative electrode and the separator. The nonaqueous electrolyte includes a lithium salt and a nonaqueous solvent in which the lithium salt is dissolved. The lithium salt concentration in the nonaqueous electrolyte present within the positive electrode is higher than the lithium salt concentration in the nonaqueous electrolyte present within the negative electrode.
    Type: Application
    Filed: May 19, 2017
    Publication date: June 13, 2019
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yuji Tani, Hajime Nishino, Yasuhiro Sugaya, Satoshi Nishitani
  • Patent number: 10186479
    Abstract: A semiconductor device includes a metal plate capacitor that includes a heat-resistant metal plate and a capacitor unit including a sintered dielectric formed on at least one surface of the heat-resistant metal plate, a semiconductor chip disposed on the metal plate capacitor, a connector configured to electrically connect the semiconductor chip and the metal plate capacitor, and a protector configured to protect the semiconductor chip, the metal plate capacitor, and the connector.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: January 22, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hidenori Katsumura, Shinya Tokunaga, Masaya Sumita, Hiroyoshi Yoshida, Yasuhiro Sugaya, Kazuhide Uriu, Osamu Shibata
  • Patent number: 9905501
    Abstract: Jitter that becomes a problem in a semiconductor part which performs high-speed signal processing is reduced. A semiconductor device includes a heat-resistant metal plate, a capacitor part having a lower electrode, a sintered dielectric part, and an upper electrode that are formed on one or more surfaces of the heat-resistant metal plate, a semiconductor chip fixed on the capacitor part, a wire for electrically connecting a lead frame to the semiconductor chip and the upper electrode, and a mold part in which at least the capacitor part and the semiconductor chip are buried. The semiconductor chip, the electrode, the metal plate, and the like are electrically connected with each other via first, second, and third wires.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: February 27, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yasuhiro Sugaya, Hidenori Katsumura, Shinya Tokunaga
  • Publication number: 20170162490
    Abstract: A semiconductor device includes a metal plate capacitor that includes a heat-resistant metal plate and a capacitor unit including a sintered dielectric formed on at least one surface of the heat-resistant metal plate, a semiconductor chip disposed on the metal plate capacitor, a connector configured to electrically connect the semiconductor chip and the metal plate capacitor, and a protector configured to protect the semiconductor chip, the metal plate capacitor, and the connector.
    Type: Application
    Filed: February 7, 2017
    Publication date: June 8, 2017
    Inventors: HIDENORI KATSUMURA, SHINYA TOKUNAGA, MASAYA SUMITA, HIROYOSHI YOSHIDA, YASUHIRO SUGAYA, KAZUHIDE URIU, OSAMU SHIBATA
  • Publication number: 20170077019
    Abstract: Jitter that becomes a problem in a semiconductor part which performs high-speed signal processing is reduced. A semiconductor device includes a heat-resistant metal plate, a capacitor part having a lower electrode, a sintered dielectric part, and an upper electrode that are formed on one or more surfaces of the heat-resistant metal plate, a semiconductor chip fixed on the capacitor part, a wire for electrically connecting a lead frame to the semiconductor chip and the upper electrode, and a mold part in which at least the capacitor part and the semiconductor chip are buried. The semiconductor chip, the electrode, the metal plate, and the like are electrically connected with each other via first, second, and third wires.
    Type: Application
    Filed: November 22, 2016
    Publication date: March 16, 2017
    Inventors: YASUHIRO SUGAYA, HIDENORI KATSUMURA, SHINYA TOKUNAGA
  • Publication number: 20140008104
    Abstract: A resistance-formed substrate includes a first insulating layer, a first wiring formed on a first surface of the first insulating layer, a thin-film resistance layer formed on a second surface of the first insulating layer, and a first via-hole conductor. The first via-hole conductor penetrates through the first insulating layer, and is electrically connected to the first wiring and the thin-film resistance layer. The first via-hole conductor includes a metal part including a low-melting point metal and a high-melting point metal, and a paste resin part. The low-melting point metal includes tin and bismuth, and has a melting point of 300° C. or lower. The high-melting point metal includes at least one of copper and silver, and has a melting point of 900° C. or higher. The first via-hole conductor is in contact with the thin-film resistance layer at both the paste resin part and the metal part.
    Type: Application
    Filed: January 29, 2013
    Publication date: January 9, 2014
    Applicant: Panasonic Corporation
    Inventors: Yasuhiro Sugaya, Hiroyuki Ishitomi, Tadashi Nakamura
  • Patent number: 7968800
    Abstract: A passive component incorporating interposer includes a double-sided circuit board (1) having a wiring layer (8) on both sides, a passive component (2) mounted on the wiring layer (8) on one surface of the double-sided circuit board (1), a second insulating layer (3) made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the surface of the double-sided circuit board (1) mounted with the passive component (2), a first insulating layer (4) made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the other surface of the double-sided circuit board (1) not mounted with the passive component (2), first and second wiring layers (5, 6) formed on the first and second insulating layers (3, 4), and a through hole (7) for electrically connecting the wiring layers (8) disposed on both surfaces of the double-sided circuit board (1) and the first and second wiring layers (5, 6), where the first wiring layer (5) is formed to enable mounting
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: June 28, 2011
    Assignee: Panasonic Corporation
    Inventors: Tatsuo Sasaoka, Yasuhiro Sugaya, Eiji Kawamoto, Kazuhiko Honjo, Toshiyuki Asahi, Chie Sasaki, Hiroaki Suzuki
  • Patent number: 7888789
    Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: February 15, 2011
    Assignee: Panasonic Corporation
    Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
  • Patent number: 7821795
    Abstract: A multilayered substrate includes a plurality of circuit boards including a plurality of wiring layers including a grounding layer and a power layer, a solid electrolytic capacitor having an insulative oxide film layer, an electrolytic layer, and a conductor layer sequentially formed on one surface or both surfaces of a foil-like metal substrate, and a conductive substance passing through the circuit board across a thickness thereof. The solid electrolytic capacitor is disposed to be held between the plurality of circuit boards. The conductor layer is connected to a grounding electrode formed on the grounding layer, the foil-like metal substrate being connected to a power electrode formed on the power layer.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: October 26, 2010
    Assignee: Panasonic Corporation
    Inventors: Yasuhiro Sugaya, Yoshiyuki Yamamoto, Toshiyuki Asahi, Katsumasa Miki, Masaaki Katsumata, Yoshiyuki Saitou, Takeshi Nakayama
  • Publication number: 20100155119
    Abstract: A passive component incorporating interposer includes a double-sided circuit board (1) having a wiring layer (8) on both sides, a passive component (2) mounted on the wiring layer (8) on one surface of the double-sided circuit board (1), a second insulating layer (3) made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the surface of the double-sided circuit board (1) mounted with the passive component (2), a first insulating layer (4) made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the other surface of the double-sided circuit board (1) not mounted with the passive component (2), first and second wiring layers (5, 6) formed on the first and second insulating layers (3, 4), and a through hole (7) for electrically connecting the wiring layers (8) disposed on both surfaces of the double-sided circuit board (1) and the first and second wiring layers (5, 6), where the first wiring layer (5) is formed to enable mounting
    Type: Application
    Filed: November 27, 2007
    Publication date: June 24, 2010
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tatsuo Sasaoka, Yasuhiro Sugaya, Eiji Kawamoto, Kazuhiko Honjo, Toshiyuki Asahi, Chie Sasaki, Hiroaki Suzuki
  • Patent number: 7667977
    Abstract: The mounting board has a capacitor-forming sheet made from a valve metal, first and second board-forming structures, first and second electrodes, an extractor electrode, and a conductive polymer. The capacitor-forming sheet has an inner layer and a rough oxide film on at least one face of the inner layer. The first board-forming structure is provided on a face of the capacitor-forming sheet, and the second board-forming structure is provided on another face thereof on a side opposite to the first one. The first and second electrodes are isolated to each other and provided on a surface of at least one of the first and second board-forming structures. The extractor electrode and conductive polymer are provided inside at least one of the first and second board-forming structures. The extractor electrode electrically-connects the first electrode with the inner layer. The conductive polymer electrically-connects the second electrode with the rough oxide film.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: February 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Yasuhiro Sugaya, Toshiyuki Asahi, Katsumasa Miki, Yoshiyuki Yamamoto, Hiroyuki Ishitomi, Tsuyoshi Himori
  • Publication number: 20080290497
    Abstract: The mounting board has a capacitor-forming sheet made from a valve metal, first and second board-forming structures, first and second electrodes, an extractor electrode, and a conductive polymer. The capacitor-forming sheet has an inner layer and a rough oxide film on at least one face of the inner layer. The first board-forming structure is provided on a face of the capacitor-forming sheet, and the second board-forming structure is provided on another face thereof on a side opposite to the first one. The first and second electrodes are isolated to each other and provided on a surface of at least one of the first and second board-forming structures. The extractor electrode and conductive polymer are provided inside at least one of the first and second board-forming structures. The extractor electrode electrically-connects the first electrode with the inner layer. The conductive polymer electrically-connects the second electrode with the rough oxide film.
    Type: Application
    Filed: July 13, 2006
    Publication date: November 27, 2008
    Inventors: Yasuhiro Sugaya, Toshiyuki Asahi, Katsumasa Miki, Yoshiyuki Yamamoto, Hiroyuki Ishitomi, Tsuyoshi Himori
  • Patent number: 7394663
    Abstract: An electronic component built-in module according to the present invention includes a pair of opposed circuit substrates, each of which includes a wiring pattern and an insulating base material containing a resin, an insulating layer that is placed between the pair of circuit substrates and contains an inorganic filler and a resin composition containing a thermosetting resin, an electronic component that is embedded in the insulating layer, and an inner via that is provided in the insulating layer so as to make an electrical connection between wiring patterns provided on different circuit substrates. A glass transition temperature Tg1 of the resin composition contained in the insulating layer and a glass transition temperature Tg2 of the insulating base material included in each of the circuit substrates satisfy a relationship Tg1>Tg2.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: July 1, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihisa Yamashita, Koichi Hirano, Yasuhiro Sugaya, Toshiyuki Asahi, Seiichi Nakatani
  • Patent number: 7390692
    Abstract: A semiconductor device (1) of the present invention includes a semiconductor element (103) including electrode parts (104), and a wiring substrate (108) including an insulation layer (101), electrode-part-connection electrodes (102) provided in the insulation layer (101), and external electrodes (107) that is provided in the insulation layer (101) and that is connected electrically with the electrode-part-connection electrodes (102), in which the electrode parts (104) and the electrode-part-connection electrodes (102) are connected electrically with each other. The insulation layer (101) has an elastic modulus measured according to JIS K6911 of not less than 0.1 GP a and not more than 5 GPa, and the electrodes (104) and the electrode-part-connection electrodes (102) are connected by metal joint.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: June 24, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Sugaya, Toshiyuki Asahi, Shingo Komatsu, Yoshiyuki Yamamoto, Seiichi Nakatani
  • Patent number: 7341890
    Abstract: A circuit board with an built-in electronic component according to the present invention includes an insulating layer, a first wiring pattern provided on a first main surface of the insulating layer, a second wiring pattern provided on a second main surface different from the first main surface of the insulating layer, and an electronic component such as a semiconductor chip or the like provided in an internal portion of the insulating layer. The electronic component includes a first external connection terminal formed on a first surface and a second external connection terminal formed on a second surface different from the first surface. The first external connection terminal is connected electrically to the first wiring pattern, and the second external connection terminal is connected electrically to the second wiring pattern.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: March 11, 2008
    Assignee: Matsushita Industrial Co., Ltd.
    Inventors: Yukihiro Ishimaru, Tousaku Nishiyama, Yasuhiro Sugaya, Toshiyuki Asahi
  • Patent number: 7294587
    Abstract: A component built-in module includes an insulating layer, wirings integrated with both surfaces of the insulating layer, a via connecting the wirings, and one or more components selected from an electronic component and a semiconductor, which is embedded inside of the insulating layer. In this module, at least one of the wirings is formed on a surface of a wiring board, and the components embedded inside of the insulating layer are mounted on and integrated with the wiring board before embedding. This configuration allows the components such as a semiconductor to undergo a mounting inspection and a property inspection before embedding. As a result, the yields of the module can be improved. In addition, since the components are integrated with the wiring board and embedded, the strength thereof can be enhanced.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: November 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiyuki Asahi, Yasuhiro Sugaya, Shingo Komatsu, Yoshiyuki Yamamoto, Seiichi Nakatani
  • Publication number: 20070242440
    Abstract: A multilayered substrate includes a plurality of circuit boards including a plurality of wiring layers including a grounding layer and a power layer, a solid electrolytic capacitor having an insulative oxide film layer, an electrolytic layer, and a conductor layer sequentially formed on one surface or both surfaces of a foil-like metal substrate, and a conductive substance passing through the circuit board across a thickness thereof. The solid electrolytic capacitor is disposed to be held between the plurality of circuit boards. The conductor layer is connected to a grounding electrode formed on the grounding layer, the foil-like metal substrate being connected to a power electrode formed on the power layer.
    Type: Application
    Filed: February 1, 2006
    Publication date: October 18, 2007
    Inventors: Yasuhiro Sugaya, Yoshiyuki Yamamoto, Toshiyuki Asahi, Katsumasa Miki, Yoshiyuki Saitou, Takeshi Nakayama
  • Publication number: 20070224735
    Abstract: A fabrication method for an optical transmission channel board includes a first step of forming on a substrate a layer containing an electrically conductive material, and a second step of patterning said layer containing an electrically conductive material formed on said substrate, and thereby forming circuit patterns at least a part of which is used as an electric circuit and at least a part of which positionally regulates an optical transmission channel.
    Type: Application
    Filed: May 18, 2007
    Publication date: September 27, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiji Karashima, Seiichi Nakatani, Yasuhiro Sugaya, Toshiyuki Asahi, Takashi Ichiryu