Patents by Inventor Yasuhiro Sugaya

Yasuhiro Sugaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060006760
    Abstract: A surface acoustic wave device which occupies a small mounting area and has a low profile, yet having an improved reliability, and can be made available at low cost. The surface acoustic wave device comprises a piezoelectric substrate, a function region formed of comb-like electrodes for exciting surface acoustic wave provided on a main surface of the piezoelectric substrate, a space formation member covering the function region, a plurality of bump electrodes provided on a main surface of the piezoelectric substrate and a terminal electrode provided opposed to the main surface of piezoelectric substrate. The bump electrode and the terminal electrode are having a direct electrical connection, and a space between piezoelectric substrate and terminal electrode is filled with resin.
    Type: Application
    Filed: September 7, 2005
    Publication date: January 12, 2006
    Inventors: Akihiko Namba, Keiji Onishi, Yasuhiro Sugaya, Katsunori Moritoki
  • Patent number: 6975516
    Abstract: A component built-in module includes an insulating layer, wirings integrated with both surfaces of the insulating layer, a via connecting the wirings, and one or more components selected from an electronic component and a semiconductor, which is embedded inside of the insulating layer. In this module, at least one of the wirings is formed on a surface of a wiring board, and the components embedded inside of the insulating layer are mounted on and integrated with the wiring board before embedding. This configuration allows the components such as a semiconductor to undergo a mounting inspection and a property inspection before embedding. As a result, the yields of the module can be improved. In addition, since the components are integrated with the wiring board and embedded, the strength thereof can be enhanced.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: December 13, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiyuki Asahi, Yasuhiro Sugaya, Shingo Komatsu, Yoshiyuki Yamamoto, Seiichi Nakatani
  • Publication number: 20050269681
    Abstract: A component built-in module includes an insulating layer, wirings integrated with both surfaces of the insulating layer, a via connecting the wirings, and one or more components selected from an electronic component and a semiconductor, which is embedded inside of the insulating layer. In this module, at least one of the wirings is formed on a surface of a wiring board, and the components embedded inside of the insulating layer are mounted on and integrated with the wiring board before embedding. This configuration allows the components such as a semiconductor to undergo a mounting inspection and a property inspection before embedding. As a result, the yields of the module can be improved. In addition, since the components are integrated with the wiring board and embedded, the strength thereof can be enhanced.
    Type: Application
    Filed: May 10, 2005
    Publication date: December 8, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiyuki Asahi, Yasuhiro Sugaya, Shingo Komatsu, Yoshiyuki Yamamoto, Seiichi Nakatani
  • Patent number: 6969945
    Abstract: A surface acoustic wave device which occupies a small mounting area and has a low profile, yet having an improved reliability, and can be made available at low cost. The surface acoustic wave device comprises a piezoelectric substrate, a function region formed of comb-like electrodes for exciting surface acoustic wave provided on a main surface of the piezoelectric substrate, a space formation member covering the function region, a plurality of bump electrodes provided on a main surface of the piezoelectric substrate and a terminal electrode provided opposed to the main surface of piezoelectric substrate. The bump electrode and the terminal electrode are having a direct electrical connection, and a space between piezoelectric substrate and terminal electrode is filled with resin.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: November 29, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Namba, Keiji Onishi, Yasuhiro Sugaya, Katsunori Moritoki
  • Patent number: 6965284
    Abstract: A dielectric filter includes resonator electrodes, an inter-stage coupling capacitor electrode, and an input/output coupling capacitor electrode on dielectric substrates, respectively. The resonator electrodes are electro-magnetically coupled to each other to form a tri-plate structure, are made of a metallic foil embedded in a resonator dielectric substrate. Another dielectric filter includes an upper shield electrode dielectric substrate, an inter-stage coupling capacitor dielectric substrate, a resonator dielectric substrate, and an input/output coupling capacitor dielectric substrate which are made of a composite dielectric material including a high-dielectric-constant material and a low-dielectric-constant material. The above described arrangement provides the dielectric filter with an improved Q factor of a resonator, a low loss, and a high attenuation.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: November 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomoya Maekawa, Yasuhiro Sugaya, Toru Yamada, Toshio Ishizaki
  • Publication number: 20050236103
    Abstract: A dielectric resonator includes a pair of dielectric substrates opposed to each other and resonator electrodes disposed between the pair of dielectric substrates. The resonator electrodes are disposed so as to be brought into contact with major surfaces of the pair of dielectric substrates, and a bonding layer is disposed around the resonator electrodes so as to bond the pair of dielectric substrates. The pair of dielectric substrates have been sintered in advance at sufficiently high temperature which is a dielectric having an fQ value at 1 GHz in the range of 3×103 to 1×105, and then achieve a high Q value as a filter. The pair of the substrates are provided with a surface roughness of a range of 0.1 to 2.0 ?m, and flatness of 10 ?m or less between both ends thereof to bring the resonant electrodes in close contact with the surfaces of the substrate.
    Type: Application
    Filed: June 9, 2005
    Publication date: October 27, 2005
    Inventors: Yasuhiro Sugaya, Tomoya Maekawa, Toru Yamada, Seiichi Nakatani
  • Publication number: 20050230848
    Abstract: A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the core layer is formed of a mixture including at least an inorganic filler and a thermosetting resin. At least one or more of active components and/or passive components are contained in an internal portion of the core layer. The core layer has a plurality of wiring patterns and a plurality of inner vias formed of a conductive resin. The electric insulating material formed of the mixture including at least an inorganic filler and a thermosetting resin of the core layer has a modulus of elasticity at room temperature in the range from 0.6 GPa to 10 GPa. Thus, it is possible to provide a thermal conductive component built-in module capable of filling the inorganic filler with high density; burying the active component such as a semiconductor etc.
    Type: Application
    Filed: June 14, 2005
    Publication date: October 20, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiichi Nakatani, Yasuhiro Sugaya, Toshiyuki Asahi, Shingo Komatsu
  • Patent number: 6955948
    Abstract: A component built-in module includes an electric insulation layer, first wiring patterns in a plurality of layers that are laminated with the electric insulation layer being interposed therebetween, at least one first inner via electrically connecting the first wiring patterns in different layers with each other, and at least one electronic component that is embedded in the electric insulation layer and is mounted on any one of the first wiring patterns in the plurality of layers, wherein at least one of the first inner vias is present in a range that overlaps a range in which the electronic component is present in a lamination direction in which the first wiring patterns are laminated, and has a height in the lamination direction that is smaller than a height of the electronic component. Since the first inner via has a small height, the via diameter can be decreased. Therefore, it is possible to provide a component built-in module that has high reliability and is suitable for high-density component mounting.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: October 18, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiyuki Asahi, Yasuhiro Sugaya, Shingo Komatsu, Seiichi Nakatani
  • Publication number: 20050196095
    Abstract: A fabrication method for an optical transmission channel board includes a first step of forming on a substrate a layer containing an electrically conductive material, and a second step of patterning said layer containing an electrically conductive material formed on said substrate, and thereby forming circuit patterns at least a part of which is used as an electric circuit and at least a part of which positionally regulates an optical transmission channel.
    Type: Application
    Filed: January 21, 2005
    Publication date: September 8, 2005
    Inventors: Seiji Karashima, Seiichi Nakatani, Yasuhiro Sugaya, Toshiyuki Asahi, Takashi Ichiryu
  • Patent number: 6939738
    Abstract: A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the core layer is formed of a mixture including at least an inorganic filler and a thermosetting resin. At least one or more of active components and/or passive components are contained in an internal portion of the core layer. The core layer has a plurality of wiring patterns and a plurality of inner vias formed of a conductive resin. The electric insulating material formed of the mixture including at least an inorganic filler and a thermosetting resin of the core layer has a modulus of elasticity at room temperature in the range from 0.6 GPa to 10 GPa. Thus, it is possible to provide a thermal conductive component built-in module capable of filling the inorganic filler with high density; burying the active component such as a semiconductor etc.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: September 6, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiichi Nakatani, Yasuhiro Sugaya, Toshiyuki Asahi, Shingo Komatsu
  • Patent number: 6936774
    Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: August 30, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
  • Publication number: 20050186768
    Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.
    Type: Application
    Filed: March 25, 2005
    Publication date: August 25, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
  • Patent number: 6931725
    Abstract: A circuit component built-in module capable of mounting the circuit component with high density and having high heat releasing property and the high reliability. The circuit component built-in module 100 includes the insulating substrate 101 made of a first mixture 105 and a second mixture 106, wiring patterns 102a and 102b formed on one principal surface and another principal surface of the insulating substrate 101, a circuit component 103a electrically connected to the wiring pattern 102a and sealed with the second mixture 106 in an internal portion of the insulating substrate 101, the inner via conductor 104 electrically connecting the wiring pattern 102a and 102b.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: August 23, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Sugaya, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Satoru Yuuhaku, Toshiyuki Asahi
  • Patent number: 6885788
    Abstract: A light reception/emission device built-in module with optical and electrical wiring combined therein includes: an optical waveguide layer including a core portion and a cladding portion; first and second wiring patterns formed on a main surface of the optical waveguide layer; a light reception device disposed inside the optical waveguide layer, the light reception device being optically connected with the core portion of the optical waveguide layer and being electrically connected with the first wiring pattern; and a light emission device disposed inside the optical waveguide layer, the light emission device being optically connected with the core portion of the optical waveguide layer and being electrically connected with the second wiring pattern. With this configuration, optical coupling between the optical waveguide and the light reception/emission device can be conducted precisely.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: April 26, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Iwaki, Yutaka Taguchi, Tetsuyoshi Ogura, Yasuhiro Sugaya, Toshiyuki Asahi, Tousaku Nishiyama, Yoshinobu Idogawa
  • Patent number: 6871396
    Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: March 29, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
  • Publication number: 20050045369
    Abstract: A circuit component built-in module includes the following: an electrical insulating substrate made of a first mixture including a filler and a thermosetting resin; a wiring pattern formed on at least a principal surface of the electrical insulating substrate; circuit components that are arranged inside the electrical insulating substrate and connected electrically to the wiring pattern; and vias for electrically connecting the wiring patterns. At least one of the circuit components is mounted using wires. Part or all of the wires is sealed with a second mixture including a filler and a resin. This circuit component built-in module can eliminate a wire failure or short circuit while using a low cost mounting technique such as wire bonding.
    Type: Application
    Filed: August 26, 2004
    Publication date: March 3, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yukihiro Ishimaru, Yasuhiro Sugaya, Toshiyuki Asahi
  • Patent number: 6855892
    Abstract: An insulation sheet for use in producing a wiring substrate comprises, as via bole conductors, conductive paste filled in via holes formed through the insulation sheet, and a curing-starting temperature of the conductive paste is lower than a melting-starting temperature of the insulation sheet. A wiring substrate is produced by laminating such insulation sheets, that have conductive paste in via holes, and subjecting this laminate to thermo-compression bonding, wherein deformation of via holes and dislocation of the via holes, because of a molten insulation sheet, does not occur.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: February 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shingo Komatsu, Seiichi Nakatani, Yasuhiro Sugaya, Toshiyuki Asahi, Yoshiyuki Yamamoto
  • Publication number: 20050006142
    Abstract: A circuit board with an built-in electronic component according to the present invention includes an insulating layer, a first wiring pattern provided on a first main surface of the insulating layer, a second wiring pattern provided on a second main surface different from the first main surface of the insulating layer, and an electronic component such as a semiconductor chip or the like provided in an internal portion of the insulating layer. The electronic component includes a first external connection terminal formed on a first surface and a second external connection terminal formed on a second surface different from the first surface. The first external connection terminal is connected electrically to the first wiring pattern, and the second external connection terminal is connected electrically to the second wiring pattern.
    Type: Application
    Filed: July 9, 2004
    Publication date: January 13, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yukihiro Ishimaru, Tousaku Nishiyama, Yasuhiro Sugaya, Toshiyuki Asahi
  • Publication number: 20050002608
    Abstract: A mount assembly with an excellent handling property which amplifies a light signal from an optical transmission line and transmits the light signal to another optical transmission line and does not require a highly precise perpendicularity at a connection portion between the optical transmission line and the mount assembly is provided. The mount assembly 100 is obtained by connecting a photo-electro conversion device 10a, spherical semiconductor devices 12a and 12b and an electro-photo conversion device 10b through electrical-connection portions 14 so that a light received by the photo-electro conversion device 10a is amplified by the spherical semiconductor devices 12a and 12b and then emitted from the electro-photo conversion device 10b.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 6, 2005
    Inventors: Tousaku Nishiyama, Yukihiro Ishimaru, Yasuhiro Sugaya, Toshiyuki Asahi, Seiji Karashima
  • Publication number: 20050001331
    Abstract: In a module with a built-in semiconductor, higher densification is achieved by disposing inner vias close to a semiconductor device. A module which has a space 107 between a first wiring layer 102a and a built-in semiconductor device 105 is obtained by: mounting the semiconductor device 105 on a first wiring layer 102a of a wiring board 103 without using a sealing resin; stacking on the circuit board an electrically insulating substrate having a through bore (inner via) 104 filled with a conductive paste and an opening for receiving the semiconductor device, and a mold release carrier having a second wiring layer 102b in the stated order; and heating and pressurizing so that the semiconductor device 105 is incorporated in a core layer 101 which is formed by curing the electrically insulating substrate.
    Type: Application
    Filed: June 22, 2004
    Publication date: January 6, 2005
    Inventors: Toshiyuki Kojima, Seiichi Nakatani, Yasuhiro Sugaya, Yoshiyuki Yamamoto