Patents by Inventor Yasuhiro Takeda

Yasuhiro Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190297922
    Abstract: A microwave-heating system irradiates sealed packaged foods with microwaves to heat the packaged foods at 100° C. or higher for heat sterilization. The microwave-heating system includes a microwave generator to irradiate the packaged foods with microwaves of 2450 MHz in a multi-mode and a microwave generator to irradiate the packaged foods in a waveguide with microwaves of 915 MHz in a single-mode.
    Type: Application
    Filed: March 12, 2019
    Publication date: October 3, 2019
    Applicant: MORINAGA MILK INDUSTRY CO., LTD.
    Inventors: Yasuhiro Takeda, Atsushi Furuya, Takahiro Koyama, Hiroyuki Ikeda, Junichi Otsuji, Shuji Obi, Yasuji Yamamoto, Junichi Kodama
  • Patent number: 10374279
    Abstract: A connector device according to the present disclosure includes a first connector section and a second connector section. The first connector section includes a waveguide for transmitting a high-frequency signal. The second connector section includes a waveguide for transmitting a high-frequency signal, a yoke disposed to cover the waveguide, and a magnet forming a magnetic circuit with the yoke, and is couplable to the first connector section by the attractive force of the magnet. A communication system according to the present disclosure includes two communication devices and a connector device. The connector device has the above-described configuration and transmits a high-frequency signal between the two communication devices.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: August 6, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Isao Matsumoto, Takayuki Mogi, Kenichi Kawasaki, Tetsuya Makita, Tatsuhito Aono, Yu Shigeta, Shintaro Nonaka, Takahiro Takeda, Yasuhiro Okada, Hiroyuki Yamagishi
  • Patent number: 10356370
    Abstract: A feature extracting unit obtains sensor data from a plurality of sensors to calculate each feature. When an event determining unit determines the occurrence of an event based on each feature, a display data constructor generates remote-controller display data for displaying the event, and controls a remote-controller display device to display the remote-controller display data. When a user decision is input from a user input IF based on this display, a control unit controls the sensors to be turned ON or OFF. When an infrared sensor detects an abnormality, a microwave sensor whose power consumption is small after the infrared sensor is turned ON. When the microwave sensor detects an abnormality, a video camera and a microphone are turned ON, and the microwave sensor is turned OFF. A communication unit wirelessly transmits an image signal captured by the video camera and an audio signal processed by the microphone.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: July 16, 2019
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Naoki Kobayashi, Yasuhiro Fujimori, Yasuaki Takahashi, Koji Ohta, Naoki Takeda
  • Patent number: 10294644
    Abstract: Afforded are: a toilet body including a toilet bowl part, a rim conduit 36, and a rim part; and a functional component mounted on an upper surface part of the toilet body, rearward of the toilet bowl part. The upper surface part includes a cut-out part formed such as to be recessed downward from the other part of the upper surface part. The functional component is disposed on the cut-out part such as to be partially positioned downward with respect to an upper surface of the rim part, and such as to be partially stuck out into the toilet bowl part from upon the cut-out part, and, on a bottom surface of the stuck-out part, the functional component is provided with a conduit forming surface serving as an upper surface of the rim conduit.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: May 21, 2019
    Assignee: LIXIL CORPORATION
    Inventors: Akiya Saeki, Hiroaki Watanabe, Yukihiro Inoue, Tooru Higashino, Masato Takeda, Akiya Oohira, Takeya Ichiyanagi, Yasuhiro Kondo, Hironao Inoue, Tetsuo Hata
  • Publication number: 20180300037
    Abstract: [Object] To make communication between users through video being distributed smoother. [Solution] There is provided an information processing device including: a communication unit configured to acquire a moving image being subjected to live distribution as well as manipulation information including a manipulation position concerning location of a sticker on the moving image being displayed on a display unit of a device and information concerning the sticker to be located; and a control unit configured to analyze a region corresponding to the manipulation position on the moving image, and perform processing of locating the sticker on the moving image on a basis of an analysis result and the manipulation information.
    Type: Application
    Filed: August 4, 2016
    Publication date: October 18, 2018
    Inventors: YASUHIRO TAKEDA, TAKESHI FUJIKI, JUNICHIRO TAKAGI
  • Publication number: 20180133951
    Abstract: The stretchable porous film of the present invention includes voids in a surface thereof, in which: the stretchable porous film has an air permeability measured with an Oken-type air permeability meter of less than 99,999 sec/100 cc; the stretchable porous film has such an extending direction that an air permeability measured with the Oken-type air permeability meter in a state in which the stretchable porous film is extended by 100% becomes less than 60,000 sec/100 cc; and the stretchable porous film has such a pulling direction that when, in a hysteresis test, the stretchable porous film is pulled from a width of 20 mm and an inter-chuck distance of 30 mm to an inter-chuck distance of 60 mm at a pulling speed of 50 mm/min and held for 1 minute, and then the pulling of the inter-chuck distance is released, a residual strain becomes 10 mm or less.
    Type: Application
    Filed: April 12, 2016
    Publication date: May 17, 2018
    Applicant: NITTO DENKO CORPORATION
    Inventors: Yasuhiro TAKEDA, Yoshitake SHIGEMATSU, Kohei TAKEDA, Shou UCHIDA, Muneshige NAKAGAWA, Shinsuke IKISHIMA
  • Publication number: 20180133357
    Abstract: Provided is a stretchable film having excellent stretchability and excellent air permeability. Also provided is an article including such stretchable film. The stretchable film of the present invention includes an olefin-based resin and a filler.
    Type: Application
    Filed: April 12, 2016
    Publication date: May 17, 2018
    Applicant: NITTO DENKO CORPORATION
    Inventors: Kohei TAKEDA, Shou UCHIDA, Muneshige NAKAGAWA, Shinsuke IKISHIMA, Yasuhiro TAKEDA, Yoshitake SHIGEMATSU
  • Patent number: 9737808
    Abstract: There is provided an information processing apparatus including an attribute management unit configured to manage a variable attribute value associated with each one or more characters existing in a real space, a detection unit configured to detect an interaction event between a first character and a real object by using an image captured by a camera that captures the real space, and a setting unit configured to set a rule for changing the attribute value of the first character depending on the interaction event. In a case where the detection unit has detected the interaction event, the attribute management unit changes the attribute value of the first character in accordance with the rule set by the setting unit.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: August 22, 2017
    Assignee: SONY CORPORATION
    Inventors: Alexis Andre, Akichika Tanaka, Yasuhiro Takeda, Tetsu Natsume, Kenichi Okada, Takatoshi Nakamura
  • Patent number: 9564540
    Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.
    Type: Grant
    Filed: July 18, 2015
    Date of Patent: February 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Uozaki, Yasuhiro Takeda, Keiichi Maekawa, Takumi Hasegawa, Kota Funayama, Yoshiki Maruyama, Kazutoshi Shiba, Shuichi Kudo
  • Patent number: 9548292
    Abstract: An ESD protection element can have a high ESD protection characteristic which has a desired breakdown voltage and flows a large discharge current. A junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N? type epitaxial layer and be connected to an anode element. An N+ type diffusion layer and a P+ typed diffusion layer connected to an surrounding the N+ type diffusion layer are formed in the N? epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as an emitted, the N? type epitaxial layer as the base, and the P+ type drawing layer etc. as the collector.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: January 17, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Seiji Otake, Yasuhiro Takeda, Yuta Miyamoto
  • Publication number: 20170010784
    Abstract: There is provided an information processing apparatus, including an icon display section which displays an icon associated to an action of a user for a purpose of the user, a selection condition acquisition section which acquires a selection condition of the icon displayed by the icon display section, and a display information generation section which generates display information for sharing selected action associated to the icon with another user by using the selection condition acquired by the selection condition acquisition section.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Applicant: Sony Corporation
    Inventor: Yasuhiro TAKEDA
  • Patent number: 9446350
    Abstract: [Object] To provide a gas decomposition apparatus and a gas decomposition method in which no safety problems occur in spite of the application of a relatively high voltage between an anode and a cathode for the purpose of decomposing odorous gases of many types. [Solution] A catalytic electrode layer 6 that contains a catalyst and is porous; a counter electrode layer 7 that forms a pair with the catalytic electrode; and an electrolyte layer 15 that is sandwiched between the catalytic electrode and the counter electrode and has ion conductivity are included. The catalyst is held by the catalytic electrode in the form of being carried by a carrier containing a conductive material or the catalyst is directly carried by the catalytic electrode. A conductive material in the catalytic electrode, the conductive material being in contact with the catalyst, is not a noncovalent carbon material.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: September 20, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masatoshi Majima, Shinji Inazawa, Koji Nitta, Masahiro Yamakawa, Takayasu Sugihara, Yasuhiro Takeda, Yoshihiro Akahane, Takahiro Imai
  • Publication number: 20160093555
    Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.
    Type: Application
    Filed: December 8, 2015
    Publication date: March 31, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Yasuhiro TAKEDA, Takao KUMIHASHI, Hiroshi YANAGITA, Takashi TAKEUCHI, Yasushi MATSUDA
  • Patent number: 9240330
    Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 19, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Takeda, Takao Kumihashi, Hiroshi Yanagita, Takashi Takeuchi, Yasushi Matsuda
  • Publication number: 20150333139
    Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.
    Type: Application
    Filed: July 18, 2015
    Publication date: November 19, 2015
    Inventors: Hiroshi Uozaki, Yasuhiro Takeda, Keiichi Maekawa, Takumi Hasegawa, Kota Funayama, Yoshiki Maruyama, Kazutoshi Shiba, Shuichi Kudo
  • Patent number: 9099552
    Abstract: The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N? type semiconductor layer. A source layer including an N? type layer is disposed in a surface portion of the body layer. An N? type drift layer is formed in a surface portion of the N? type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: August 4, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yasuhiro Takeda, Shinya Inoue, Yuzo Otsuru
  • Patent number: 9093546
    Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: July 28, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Uozaki, Yasuhiro Takeda, Keiichi Maekawa, Takumi Hasegawa, Kota Funayama, Yoshiki Maruyama, Kazutoshi Shiba, Shuichi Kudo
  • Publication number: 20150080125
    Abstract: There is provided an information processing apparatus including an attribute management unit configured to manage a variable attribute value associated with each one or more characters existing in a real space, a detection unit configured to detect an interaction event between a first character and a real object by using an image captured by a camera that captures the real space, and a setting unit configured to set a rule for changing the attribute value of the first character depending on the interaction event. In a case where the detection unit has detected the interaction event, the attribute management unit changes the attribute value of the first character in accordance with the rule set by the setting unit.
    Type: Application
    Filed: March 7, 2013
    Publication date: March 19, 2015
    Inventors: Alexis Andre, Akichika Tanaka, Yasuhiro Takeda, Tetsu Natsume, Kenichi Okada, Takatoshi Nakamura
  • Patent number: 8916931
    Abstract: An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: December 23, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yasuhiro Takeda, Seiji Otake
  • Publication number: 20140247527
    Abstract: An ESD protection element can have a high ESD protection characteristic which has a desired breakdown voltage and flows a large discharge current. A junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N? type epitaxial layer and be connected to an anode element. An N+ type diffusion layer and a P+ typed diffusion layer connected to an surrounding the N+ type diffusion layer are formed in the N? epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as an emitted, the N? type epitaxial layer as the base, and the P+ type drawing layer etc. as the collector.
    Type: Application
    Filed: May 16, 2014
    Publication date: September 4, 2014
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Seiji OTAKE, Yasuhiro TAKEDA, Yuta MIYAMOTO