Patents by Inventor Yasuhiro Takeda

Yasuhiro Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8525259
    Abstract: The invention prevents a source-drain breakdown voltage of a DMOS transistor from decreasing due to dielectric breakdown in a portion of a N type drift layer having high concentration formed in an active region near field oxide film corner portions surrounding an gate width end portion. The field oxide film corner portions are disposed on the outside of the gate width end portion so as to be further away from a P type body layer formed in the gate width end portion by forming the active region wider on the outside of the gate width end portion than in a gate width center portion. By this, the N type drift layer having high concentration near the field oxide film corner portions are disposed further away from the P type body layer without increasing the device area.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: September 3, 2013
    Assignees: Semiconductor Components Industries, LLC., SANYO Semiconductor Co., Ltd.
    Inventors: Yasuhiro Takeda, Kazunori Fujita, Haruki Yoneda
  • Patent number: 8450810
    Abstract: An ON resistance of a bidirectional switch with a trench gate structure composed of two MOS transistors sharing a common drain is reduced. A plurality of trenches is formed in an N type well layer. Then a P type body layer is formed in every other column of the N type well layer interposed between a pair of the trenches. A first N+ type source layer and a second N+ type source layer are formed alternately in each of a plurality of the P type body layers. A first gate electrode is formed in each of a pair of the trenches interposing the first N+ type source layer, and a second gate electrode is formed in each of a pair of the trenches interposing the second N+ type source layer.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: May 28, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Yasuhiro Takeda
  • Patent number: 8420128
    Abstract: An agent for thermally stabilizing lactoferrin, which comprises a nucleic acid as an active ingredient, can be added to lactoferrin to impart thermal stability to lactoferrin. Thermally stabilized lactoferrin can be heat-sterilized at a pH value around a neutral pH value while keeping its activity.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: April 16, 2013
    Assignee: Morinaga Milk Industry Co., Ltd.
    Inventors: Ayako Horigome, Mai Murata, Koji Yamauchi, Mitsunori Takase, Yasuhiro Takeda, Junichi Hashimoto, Ikumi Kojima
  • Publication number: 20130075864
    Abstract: An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a P+ type buried layer and a parasitic PNP bipolar transistor which uses a P+ type drawing layer connected to a P+ type diffusion layer as the emitter, an N? type epitaxial layer as the base, and a P type semiconductor substrate as the collector. The P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer connected to and surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, the parasitic PNP bipolar transistor turns on to flow a large discharge current.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 28, 2013
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Seiji OTAKE, Yasuhiro TAKEDA, Yuta MIYAMOTO
  • Publication number: 20130075865
    Abstract: An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a first P+ type buried layer and a parasitic PNP bipolar transistor which uses a second P+ type buried layer connected to a P+ type diffusion layer as the emitter, an N? type epitaxial layer as the base, and the first P+ type buried layer as the collector. The first P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, and the parasitic PNP bipolar transistor turns on to flow a large discharge current.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 28, 2013
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Seiji OTAKE, Yasuhiro TAKEDA, Yuta MIYAMOTO
  • Publication number: 20130075866
    Abstract: A PN junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N? type epitaxial layer and be connected to an anode electrode. An N+ type diffusion layer and a P+ type diffusion layer connected to and surrounding the N+ type diffusion layer are formed in the N? type epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and the P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as the emitter, the N? type epitaxial layer as the base, and the P+ type drawing layer etc as the collector.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 28, 2013
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Seiji Otake, Yasuhiro Takeda, Yuta Miyamoto
  • Patent number: 8395210
    Abstract: The invention provides a DMOS transistor in which a leakage current is decreased and the source-drain breakdown voltage of the transistor in the off state is enhanced when a body layer is formed by oblique ion implantation. After a photoresist layer 18 is formed, using the photoresist layer 18 and a gate electrode 14 as a mask, first ion implantation is performed toward a first corner portion 14C1 on the inside of the gate electrode 14 in a first direction shown by an arrow A?. A first body layer 17A? is formed by this first ion implantation. The first body layer 17A? is formed so as to extend from the first corner portion 14C1 to under the gate electrode 14, and the P-type impurity concentration of the body layer 17A? in the first corner portion 14C1 is higher than that of a conventional transistor.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: March 12, 2013
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Yasuhiro Takeda, Seiji Otake, Shuichi Kikuchi
  • Publication number: 20120326235
    Abstract: A semiconductor device equally turns on the parasitic bipolar transistors in the finger portions of the finger form source and drain electrodes when a surge voltage is applied, even with the P+ type contact layer surrounding the N+ type source layers and the N+ type drain layers connected to the finger form source and drain electrodes. A P+ type contact layer surrounds N+ type source layers and N+ type drain layers. Metal silicide layers are formed on the N+ type source layers, the N+ type drain layers, and a portion of the P+ type contact layer. Finger form source electrodes, finger form drain electrodes, and a P+ type contact electrode surrounding these finger form electrodes are formed, being connected to the metal silicide layers respectively through contact holes formed in an interlayer insulation film deposited on the metal silicide layers.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 27, 2012
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Yuzo OTSURU, Yasuhiro Takeda, Shigeyuki Sugihara, Shinya Inoue
  • Publication number: 20120318253
    Abstract: Disclosed is a porous film for a bag-constituting member prepared by stretching an unstretched film to be porous. The unstretched film is made from a material composition essentially including a linear low-density polyethylene; an olefinic copolymer having a Vicat softening point of from 20° C. to 50° C. and a density of less than 0.900 g/cm3; and an inorganic filler. The porous film excels in low-temperature heat sealability and gives a bag-constituting member for a body warmer.
    Type: Application
    Filed: June 1, 2012
    Publication date: December 20, 2012
    Applicant: NITTO LIFETEC CORPORATION
    Inventors: Hiroshi Nagami, Yasuhiro Takeda
  • Patent number: 8230988
    Abstract: An apparatus for transferring vehicles onto a conveyer comprises: a front wheel supporting device (6) on an elevator (5), which is provided with a pair of front and rear wheel supporting arms (29a, 29b) that freely open and close in a horizontal direction between a closed posture supporting front wheels (Wf) at a predetermined position in terms of the convey direction and an opened posture releasing the front wheels (Wf) to the convey direction; a rear wheel supporting device (7) on the elevator (5), which is provided with a wheel supporting plate (38) that supports rear wheels (Wr) without determining the position thereof in terms of the convey direction and can switch its posture between a horizontal posture and a front-down tilted posture in terms of the convey direction; and a posture switching device (40) that changes the wheel supporting plate (38) of the rear wheel supporting device (7) to the tilted posture, at least when the elevator (5), supporting a vehicle (C) with the wheel supporting arms (29a,
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: July 31, 2012
    Assignees: Daifuku Co., Ltd., Honda Motor Co., Ltd.
    Inventors: Shoji Tada, Yoshifumi Yasuda, Junichi Miura, Yasuhiro Takeda
  • Publication number: 20120126324
    Abstract: The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N? type semiconductor layer. A source layer including an N? type layer is disposed in a surface portion of the body layer. An N? type drift layer is formed in a surface portion of the N? type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region.
    Type: Application
    Filed: November 23, 2011
    Publication date: May 24, 2012
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Yasuhiro TAKEDA, Shinya Inoue, Yuzo Otsuru
  • Publication number: 20120112240
    Abstract: An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 10, 2012
    Applicant: ON Semiconductor Trading, Ltd.
    Inventors: Yasuhiro TAKEDA, Seiji OTAKE
  • Patent number: 8110463
    Abstract: A method of fabricating a semiconductor device includes a first step of forming a defect suppression film suppressing increase in a defect due to implantation of an impurity on a semiconductor substrate, a second step of forming an active region on a surface of the semiconductor substrate by implanting the impurity through the defect suppression film, a third step of removing the defect suppression film and a fourth step of forming an interface state suppression film suppressing increase in an interface state density of the active region on the active region.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: February 7, 2012
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Satoru Shimada, Yasuhiro Takeda, Seiji Otake
  • Publication number: 20120025305
    Abstract: An ON resistance of a bidirectional switch with a trench gate structure composed of two MOS transistors sharing a common drain is reduced. A plurality of trenches is formed in an N type well layer. Then a P type body layer is formed in every other column of the N type well layer interposed between a pair of the trenches. A first N+ type source layer and a second N+ type source layer are formed alternately in each of a plurality of the P type body layers. A first gate electrode is formed in each of a pair of the trenches interposing the first N+ type source layer, and a second gate electrode is formed in each of a pair of the trenches interposing the second N+ type source layer.
    Type: Application
    Filed: July 21, 2011
    Publication date: February 2, 2012
    Applicant: ON Semiconductor Trading, Ltd., a Bermuda limited liability company
    Inventor: Yasuhiro TAKEDA
  • Publication number: 20110293202
    Abstract: It is aimed to provide a spout member and a packaging bag using the spout member which have excellent handling property and hygiene management performance at the time of supplying water or the like from the outside before and during use such as administration of water and medicine, in which a closure means for freely opening and closing an aperture formed by cutting off parts of peripheral portions of sealed film pieces is protected from a contained content at the time of storage or transportation and which have excellent protecting property even when an inner pressure acts in the packaging bag, excellent contamination preventing property until a spout is opened and excellent contamination preventing property and handling property after opening.
    Type: Application
    Filed: September 1, 2009
    Publication date: December 1, 2011
    Applicants: FUJIMORI KOGYO CO., LTD., MORINAGA MILK INDUSTRY CO., LTD.
    Inventors: Yasuhiro Takeda, Kenji Washida, Takahiro Koyama, Tetsushi Mori, Yasuharu Takada, Moritoshi Oguni, Hirotaka Ikeda, Toshihiko Mori, Matsutarou Ono
  • Patent number: 8035444
    Abstract: An amplifier capable of lowering an electrical current flowing in a peak amplifier before a carrier amplifier becomes saturated to thereby improve the efficiency of an entirety of the amplifier is provided. The amplifier includes a carrier amplifier circuit having an amplifying element operable in class-AB or class-B, and a plurality of peak amplifier circuits which have amplifying elements operating in class-B or class-C and which are arranged to start an operation in stages in response to an input level. An output of the carrier amplifier circuit and outputs of the peak amplifier circuits are combined together for signal output. One of the peak amplifier circuits which is rendered operative at the lowest input level is smaller in saturation output than the carrier amplifier circuit.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: October 11, 2011
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yoichi Okubo, Manabu Nakamura, Yasuhiro Takeda, Taizo Ito, Junya Dosaka, Terufumi Nagano, Hidekatsu Ueno, Toshio Nojima
  • Patent number: 8030995
    Abstract: A power circuit used for an amplifier, which includes an amplifier provided with a linear amplifier serving as a voltage source, a DC/DC converter serving as a current source, a hysteresis comparator controlling the DC/DC converter, and a current detector detecting output current from the linear amplifier to output the detected output current to the hysteresis comparator; and a switching restricting device for restricting a switching interval in the DC/DC converter such that the switching interval is not equal to or less than a constant time or is not shorter than the constant time.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: October 4, 2011
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yoichi Okubo, Manabu Nakamura, Junya Dosaka, Yasuhiro Takeda, Taizo Ito, Naoki Hongo, Taizo Yamawaki, Takashi Kawamoto, Akira Maeki
  • Patent number: 8022475
    Abstract: An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a semiconductor substrate, respectively. A first buried layer is formed between the first region of the semiconductor substrate and the first region of the semiconductor layer, while a second buried layer is formed between the second region of the semiconductor substrate and the second region of the semiconductor layer. The first buried layer is formed of an N+ type first impurity-doped layer and an N type second impurity-doped layer that extends beyond the fist impurity-doped layer. The second buried layer is formed of an N+ type impurity-doped layer only. In the first region of the semiconductor layer, an impurity is diffused from a surface of the semiconductor layer deep into the semiconductor layer to form an N type third impurity-doped layer.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: September 20, 2011
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Yasuhiro Takeda, Seiji Otake, Kazunori Fujita
  • Patent number: 8014443
    Abstract: The present invention provides a non-linear distortion detection method and a distortion compensation amplifying device capable of suppressing increase of the circuit size and the power consumption even if the signal band is widened. A signal obtained by feeding back an output of a power amplifier is sampled by an A/D converter. An equalizer of a distortion detection unit uses an input signal d(n) of a predistorter as a reference symbol to detect an equalization error e(n) of the orthogonal demodulation signal u(n). An absolute value averaging unit outputs an absolute value of the equalization error e(n) which has been temporally averaged to E(n) as a distortion value to a control unit. According to the distortion value, the control unit adaptively controls the predistorter to perform distortion compensation.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: September 6, 2011
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Manabu Nakamura, Yasuhiro Takeda, Yoichi Okubo, Masaru Adachi, Naoki Hongo
  • Publication number: 20110132692
    Abstract: An apparatus for transferring vehicles onto a conveyer comprises: a front wheel supporting means (6) on an elevator (5), which is provided with a pair of front and rear wheel supporting arms (29a, 29b) that freely open and close in a horizontal direction between a closed posture supporting front wheels (Wf) at a predetermined position in terms of the convey direction and an opened posture releasing the front wheels (Wf) to the convey direction; a rear wheel supporting means (7) on the elevator (5), which is provided with a wheel supporting plate (38) that supports rear wheels (Wr) without determining the position thereof in terms of the convey direction and can switch its posture between a horizontal posture and a front-down tilted posture in terms of the convey direction; and a posture switching means (40) that changes the wheel supporting plate (38) of the rear wheel supporting means (7) to the tilted posture, at least when the elevator (5), supporting a vehicle (C) with the wheel supporting arms (29a, 29b)
    Type: Application
    Filed: March 2, 2009
    Publication date: June 9, 2011
    Applicants: Daifuku Co., Ltd., Honda Motor Co., Ltd.
    Inventors: Shoji Tada, Yoshifumi Yasuda, Junichi Miura, Yasuhiro Takeda