Patents by Inventor Yasuhiro Taniguchi

Yasuhiro Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190202447
    Abstract: A parking assistance method including: setting a target parking position of a vehicle on the basis of a circumferential situation of the vehicle detected by a circumferential situation detection sensor; determining a communication situation between an operation device configured to receive an operation by an operator outside the vehicle and transmit an instruction signal corresponding to the operation and a communication device mounted on the vehicle and configured to receive the instruction signal; limiting the operation for manually adjusting the target parking position in the operation device depending on the communication situation; transmitting, when the target parking position is adjusted, the instruction signal for moving the target parking position to the communication device; and parking the vehicle by the automatic driving in the target parking position moved depending on the instruction signal received at the communication device.
    Type: Application
    Filed: September 6, 2016
    Publication date: July 4, 2019
    Applicant: Nissan Motor Co., Ltd.
    Inventors: Yohei Taniguchi, Yasuhisa Hayakawa, Yasuhiro Suzuki, Ichiro Yamaguchi
  • Publication number: 20190197322
    Abstract: A method of determining obstacles determines if a detected object detected outside a subject vehicle is an obstacle for the subject vehicle on the basis of a predetermined determination criterion. In this method, a determination is made whether or not the detected object detected outside the subject vehicle is a driver or passenger of the subject vehicle. When the detected object is not the driver or passenger, a determination is made whether or not the detected object is an obstacle for the subject vehicle on the basis of a first determination criterion. When the detected object is the driver or passenger, a determination is made whether or not the detected object is an obstacle for the subject vehicle on the basis of a second determination criterion with which the detected object is less likely to be determined as an obstacle for the subject vehicle than with the first determination criterion.
    Type: Application
    Filed: September 6, 2016
    Publication date: June 27, 2019
    Inventors: Yasuhiro Suzuki, Yasuhisa Hayakawa, Yohei Taniguchi
  • Patent number: 10276727
    Abstract: A semiconductor integrated circuit device includes first and second select gate electrodes that are sidewall-shaped along sidewalls of a memory gate structure. With this configuration, the memory gate structure is not disposed on the first select gate electrode and the second select gate electrode. Accordingly, the memory gate structure the first select gate structure, and the second select gate structure can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer on the first select gate electrode and a silicide layer on the second select gate electrode can be separated farther from a memory gate electrode by the thickness of a cap film. Accordingly, the silicide layers on the first select gate electrode and the second select gate electrode are unlikely to contact with the memory gate electrode, thereby preventing a short-circuit defect of the memory gate electrode.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 30, 2019
    Assignee: FLOADIA CORPORATION
    Inventors: Fukuo Owada, Yasuhiko Kawashima, Shinji Yoshida, Yasuhiro Taniguchi, Kosuke Okuyama
  • Patent number: 10263002
    Abstract: In an anti-fuse memory includes a rectifier element of a semiconductor junction structure in which a voltage applied from a memory gate electrode to a word line is applied as a reverse bias in accordance with voltage values of the memory gate electrode and the word line, and does not use a conventional control circuit. Hence, the rectifier element blocks application of a voltage from the memory gate electrode to the word line. Therefore a conventional switch transistor that selectively applies a voltage to a memory capacitor and a conventional switch control circuit allowing the switch transistor to turn on or off are not necessary. Miniaturization of the anti-fuse memory and a semiconductor memory device are achieved correspondingly.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: April 16, 2019
    Assignee: FLOADIA CORPORATION
    Inventors: Yasuhiro Taniguchi, Hideo Kasai, Yasuhiko Kawashima, Ryotaro Sakurai, Yutaka Shinagawa, Kosuke Okuyama
  • Publication number: 20180308990
    Abstract: A semiconductor integrated circuit device includes first and second select gate electrodes that are sidewall-shaped along sidewalls of a memory gate structure. With this configuration, the memory gate structure is not disposed on the first select gate electrode and the second select gate electrode. Accordingly, the memory gate structure the first select gate structure, and the second select gate structure can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer on the first select gate electrode and a silicide layer on the second select gate electrode can be separated farther from a memory gate electrode by the thickness of a cap film. Accordingly, the silicide layers on the first select gate electrode and the second select gate electrode are unlikely to contact with the memory gate electrode, thereby preventing a short-circuit defect of the memory gate electrode.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 25, 2018
    Inventors: Fukuo OWADA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Yasuhiro TANIGUCHI, Kosuke OKUYAMA
  • Patent number: 10102911
    Abstract: A non-volatile semiconductor memory device in which, while voltage from a first control line is applied, as a memory gate voltage, to a sub control line through a switching transistor, another switching transistor can block voltage application to a corresponding sub control line. Thus, while a plurality of memory cells are arranged in one direction along the first control line, the number of memory cells to which a memory gate voltage is applied can reduced by the switching transistor, which reduces the occurrence of disturbance, accordingly. The sub control line to which the memory gate voltage is applied from the first control line is used as the gates of memory transistors, and thus the sub control line and the gates are disposed in a single wiring layer, thereby achieving downsizing as compared to a case in which the sub control line and the gates are disposed in separate wiring layers.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: October 16, 2018
    Assignee: FLOADIA CORPORATION
    Inventors: Hideo Kasai, Yasuhiro Taniguchi, Yutaka Shinagawa, Ryotaro Sakurai, Yasuhiko Kawashima, Kosuke Okuyama
  • Publication number: 20180286875
    Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.
    Type: Application
    Filed: December 7, 2016
    Publication date: October 4, 2018
    Applicant: Floadia Corporation
    Inventors: Daisuke OKADA, Kazumasa YANAGISAWA, Fukuo OWADA, Shoji YOSHIDA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Yasuhiro TANIGUCHI, Kosuke OKUYAMA
  • Patent number: 10074658
    Abstract: A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM to a non-volatile memory unit through fast operation of the SRAM are disclosed. A non-volatile semiconductor memory device can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit. Thus, a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor included in the SRAM connected with the non-volatile memory unit can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM at a lower power supply voltage.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: September 11, 2018
    Assignee: FLOADIA CORPORATION
    Inventors: Yutaka Shinagawa, Yasuhiro Taniguchi, Hideo Kasai, Ryotaro Sakurai, Yasuhiko Kawashima, Tatsuro Toya, Kosuke Okuyama
  • Patent number: 10074660
    Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 11, 2018
    Assignee: FLOADIA CORPORATION
    Inventors: Hideo Kasai, Yasuhiro Taniguchi, Yasuhiko Kawashima, Ryotaro Sakurai, Yutaka Shinagawa, Tatsuro Toya, Takanori Yamaguchi, Fukuo Owada, Shinji Yoshida, Teruo Hatada, Satoshi Noda, Takafumi Kato, Tetsuya Muraya, Kosuke Okuyama
  • Patent number: 10038101
    Abstract: A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: July 31, 2018
    Assignee: FLOADIA CORPORATION
    Inventors: Yutaka Shinagawa, Yasuhiro Taniguchi, Hideo Kasai, Ryotaro Sakurai, Yasuhiko Kawashima, Tatsuro Toya, Kosuke Okuyama
  • Publication number: 20180211965
    Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.
    Type: Application
    Filed: July 21, 2016
    Publication date: July 26, 2018
    Inventors: Shoji YOSHIDA, Fukuo OWADA, Daisuke OKADA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Kazumasa YANAGISAWA, Yasuhiro TANIGUCHI
  • Publication number: 20180197958
    Abstract: A semiconductor integrated circuit device includes first and second select gate electrodes that are sidewall-shaped along sidewalls of a memory gate structure. With this configuration, the memory gate structure is not disposed on the first select gate electrode and the second select gate electrode. Accordingly, the memory gate structure the first select gate structure, and the second select gate structure can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer on the first select gate electrode and a silicide layer on the second select gate electrode can be separated farther from a memory gate electrode by the thickness of a cap film. Accordingly, the silicide layers on the first select gate electrode and the second select gate electrode are unlikely to contact with the memory gate electrode, thereby preventing a short-circuit defect of the memory gate electrode.
    Type: Application
    Filed: May 27, 2016
    Publication date: July 12, 2018
    Inventors: Yasuhiro TANIGUCHI, Fukuo OWADA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Kosuke OKUYAMA
  • Publication number: 20180083014
    Abstract: A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM to a non-volatile memory unit through fast operation of the SRAM are disclosed. A non-volatile semiconductor memory device can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit. Thus, a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor included in the SRAM connected with the non-volatile memory unit can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM at a lower power supply voltage.
    Type: Application
    Filed: March 18, 2016
    Publication date: March 22, 2018
    Inventors: Yutaka SHINAGAWA, Yasuhiro TANIGUCHI, Hideo KASAI, Ryotaro SAKURAI, Yasuhiko KAWASHIMA, Tatsuro TOYA, Kosuke OKUYAMA
  • Publication number: 20180019248
    Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.
    Type: Application
    Filed: February 19, 2016
    Publication date: January 18, 2018
    Inventors: Hideo KASAI, Yasuhiro TANIGUCHI, Yasuhiko KAWASHIMA, Ryotaro SAKURAI, Yutaka SHINAGAWA, Tatsuro TOYA, Takanori YAMAGUCHI, Fukuo OWADA, Shinji YOSHIDA, Teruo HATADA, Satoshi NODA, Takafumi KATO, Tetsuya MURAYA, Kosuke OKUYAMA
  • Patent number: 9842650
    Abstract: A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell M1a or the second memory cell M1b. Thus memory capacity is increased.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: December 12, 2017
    Assignee: FLOADIA CORPORATION
    Inventors: Yasuhiro Taniguchi, Yutaka Shinagawa, Hideo Kasai, Ryotaro Sakurai, Tatsuro Toya, Yasuhiko Kawashima, Kosuke Okuyama
  • Publication number: 20170352425
    Abstract: A non-volatile semiconductor memory device in which, while voltage from a first control line is applied, as a memory gate voltage, to a sub control line through a switching transistor, another switching transistor can block voltage application to a corresponding sub control line. Thus, while a plurality of memory cells are arranged in one direction along the first control line, the number of memory cells to which a memory gate voltage is applied can reduced by the switching transistor, which reduces the occurrence of disturbance, accordingly. The sub control line to which the memory gate voltage is applied from the first control line is used as the gates of memory transistors, and thus the sub control line and the gates are disposed in a single wiring layer, thereby achieving downsizing as compared to a case in which the sub control line and the gates are disposed in separate wiring layers.
    Type: Application
    Filed: December 11, 2015
    Publication date: December 7, 2017
    Inventors: Hideo Kasai, Yasuhiro Taniguchi, Yutaka Shinagawa, Ryotaro Sakurai, Yasuhiko Kawashima, Kosuke Okuyama
  • Patent number: 9830989
    Abstract: In a memory unit, voltages required for operations of a capacity transistor in a first well and a writing transistor in a second well are separately applied to a first deep well and a second deep well, without the voltages on the first deep well and the second deep well being restricted by each other. Thus, in the memory unit, each of a voltage difference between the first deep well and the first well and a voltage difference between the second deep well and the second well is made smaller than a voltage difference (18 [V]), at which a tunneling effect occurs, and accordingly a junction voltage between the first deep well and the first well and a junction voltage between the second deep well and the second well are low.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: November 28, 2017
    Assignee: FLOADIA CORPORATION
    Inventors: Yutaka Shinagawa, Hideo Kasai, Yasuhiko Kawashima, Ryotaro Sakurai, Yasuhiro Taniguchi
  • Publication number: 20170250187
    Abstract: In an anti-fuse memory includes a rectifier element of a semiconductor junction structure in which a voltage applied from a memory gate electrode to a word line is applied as a reverse bias in accordance with voltage values of the memory gate electrode and the word line, and does not use a conventional control circuit. Hence, the rectifier element blocks application of a voltage from the memory gate electrode to the word line. Therefore a conventional switch transistor that selectively applies a voltage to a memory capacitor and a conventional switch control circuit allowing the switch transistor to turn on or off are not necessary. Miniaturization of the anti-fuse memory and a semiconductor memory device are achieved correspondingly.
    Type: Application
    Filed: October 9, 2015
    Publication date: August 31, 2017
    Inventors: Yasuhiro TANIGUCHI, Hideo KASAI, Yasuhiko KAWASHIMA, Ryotaro SAKURAI, Yutaka SHINAGAWA, Kosuke OKUYAMA
  • Publication number: 20170221563
    Abstract: A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell M1a or the second memory cell M1b. Thus memory capacity is increased.
    Type: Application
    Filed: July 22, 2015
    Publication date: August 3, 2017
    Inventors: Yasuhiro Taniguchi, Yutaka Shinagawa, Hideo Kasai, Ryotaro Sakurai, Tatsuro Toya, Yasuhiko Kawashima, Kosuke Okuyama
  • Publication number: 20170222036
    Abstract: A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.
    Type: Application
    Filed: October 6, 2015
    Publication date: August 3, 2017
    Inventors: Yutaka Shinagawa, Yasuhiro Taniguchi, Hideo Kasai, Ryotaro Sakurai, Yasuhiko Kawashima, Tatsuro Toya, Kosuke Okuyama