Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

Abstract: A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM to a non-volatile memory unit through fast operation of the SRAM are disclosed. A non-volatile semiconductor memory device can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit. Thus, a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor included in the SRAM connected with the non-volatile memory unit can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM at a lower power supply voltage.

Abstract: A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.

Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.

Abstract: A semiconductor integrated circuit device includes first and second select gate electrodes that are sidewall-shaped along sidewalls of a memory gate structure. With this configuration, the memory gate structure is not disposed on the first select gate electrode and the second select gate electrode. Accordingly, the memory gate structure the first select gate structure, and the second select gate structure can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer on the first select gate electrode and a silicide layer on the second select gate electrode can be separated farther from a memory gate electrode by the thickness of a cap film. Accordingly, the silicide layers on the first select gate electrode and the second select gate electrode are unlikely to contact with the memory gate electrode, thereby preventing a short-circuit defect of the memory gate electrode.

Abstract: A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM to a non-volatile memory unit through fast operation of the SRAM are disclosed. A non-volatile semiconductor memory device can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit. Thus, a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor included in the SRAM connected with the non-volatile memory unit can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM at a lower power supply voltage.

Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

Abstract: A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell M1a or the second memory cell M1b. Thus memory capacity is increased.

Abstract: A non-volatile semiconductor memory device in which, while voltage from a first control line is applied, as a memory gate voltage, to a sub control line through a switching transistor, another switching transistor can block voltage application to a corresponding sub control line. Thus, while a plurality of memory cells are arranged in one direction along the first control line, the number of memory cells to which a memory gate voltage is applied can reduced by the switching transistor, which reduces the occurrence of disturbance, accordingly. The sub control line to which the memory gate voltage is applied from the first control line is used as the gates of memory transistors, and thus the sub control line and the gates are disposed in a single wiring layer, thereby achieving downsizing as compared to a case in which the sub control line and the gates are disposed in separate wiring layers.

Abstract: In a memory unit, voltages required for operations of a capacity transistor in a first well and a writing transistor in a second well are separately applied to a first deep well and a second deep well, without the voltages on the first deep well and the second deep well being restricted by each other. Thus, in the memory unit, each of a voltage difference between the first deep well and the first well and a voltage difference between the second deep well and the second well is made smaller than a voltage difference (18 [V]), at which a tunneling effect occurs, and accordingly a junction voltage between the first deep well and the first well and a junction voltage between the second deep well and the second well are low.

Abstract: In an anti-fuse memory includes a rectifier element of a semiconductor junction structure in which a voltage applied from a memory gate electrode to a word line is applied as a reverse bias in accordance with voltage values of the memory gate electrode and the word line, and does not use a conventional control circuit. Hence, the rectifier element blocks application of a voltage from the memory gate electrode to the word line. Therefore a conventional switch transistor that selectively applies a voltage to a memory capacitor and a conventional switch control circuit allowing the switch transistor to turn on or off are not necessary. Miniaturization of the anti-fuse memory and a semiconductor memory device are achieved correspondingly.

Abstract: A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell M1a or the second memory cell M1b. Thus memory capacity is increased.

Abstract: A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.

Abstract: In the non-volatile semiconductor memory device, a mobile charge collector layer, a mobile charge collecting contact, a mobile charge collecting first wiring layer, an in-between contact between the mobile charge collector layers, and a mobile charge collecting second wiring layer are disposed adjacent to a floating gate. Thereby, without increasing areas of active regions in the non-volatile semiconductor memory device, the number of mobile charges collected near the floating gate is reduced. The non-volatile semiconductor memory device allows high-speed operation of a memory cell while reducing fluctuations in a threshold voltage of the memory cell caused by collection of the mobile charges, which are attracted from an insulation layer, near the floating gate.

Abstract: To propose a non-volatile semiconductor memory device capable of injecting charge into a floating gate by source side injection even in a single-layer gate structure. In a non-volatile semiconductor memory device (1), while each of the memory transistor (MGA1) and the switch transistor (SGA) is made to have a single-layer gate structure, when a selected memory cell (3a) is turned on by applying a high voltage to one end of a memory transistor (MGA1) from a source line (SL) during data programming and applying a low voltage to one end of the switch transistor (SGA) from a bit line (BL1), a voltage drop occurs in a low-concentration impurity extension region (ET2) in the memory transistor (MGA1) between the source line (SL) and the bit line (BL1) to generate an intense electric field, and charge can be injected into the floating gate (FG) by source side injection using the intense electric field.

Abstract: In a memory unit, voltages required for operations of a capacity transistor in a first well and a writing transistor in a second well are separately applied to a first deep well and a second deep well, without the voltages on the first deep well and the second deep well being restricted by each other. Thus, in the memory unit, each of a voltage difference between the first deep well and the first well and a voltage difference between the second deep well and the second well is made smaller than a voltage difference (18 [V]), at which a tunneling effect occurs, and accordingly a junction voltage between the first deep well and the first well and a junction voltage between the second deep well and the second well are low.

Abstract: Provided is a non-volatile semiconductor memory device capable of reliably preventing a malfunction of a read transistor without increasing the number of bit lines. In a non-volatile semi conductor memory device (1), program transistors (5a, 5b) and erase transistors (3a, 3b) serving as charge transfer paths during data programming and erasure are provided while a second bit line (BLN1) connected to the program transistor (5a) in a first cell (2a) for performing data programming also serves as a reading bit line in the other second cell (2b) by switching switch transistors (SWa, SWb) so that malfunctions of read transistors (4a, 4b) that occur because the read transistors are used for data programming and erasure can be reliably prevented without the number of bit lines being increased.

Abstract: In a non-volatile semiconductor memory device, it is only necessary that, at the time of data writing, a voltage drop is caused in a high resistance region. Therefore, the value of voltage applied to a gate electrode can be reduced as compared with a conventional device. In correspondence with the reduction in the value of applied voltage, it is possible to reduce the film thickness of a gate insulating film of memory transistors, and further the film thickness of the gate insulating film of a peripheral transistor for controlling the memory transistors. As a result, the circuit configuration of the non-volatile semiconductor memory device can be reduced in size as compared with the conventional device.

Abstract: A non-volatile semiconductor memory device is proposed that has an unprecedented novel structure in which carriers can be injected into a floating gate by applying various voltages of the same polarity.

Abstract: A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (1), when a selected memory cell transistor (115) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a PMOS transistor (9b) while low voltage as writing voltage is applied from an NMOS transistor (15a). Thus, a role of applying voltage to either the selected memory cell transistor (115) or a non-selected memory cell transistor (116) is shared by the PMOS transistor (9b) and the NMOS transistor (15a). Therefore, the gate voltage and the source voltage of the PMOS transistor (9b) and those of the NMOS transistor (15a) can be separately adjusted, and gate-to-substrate voltage thereof can be finally set to be, for instance, 4[V] or etc.