Abstract: A semiconductor memory and a partial writing method are provided. The semiconductor memory includes a memory bank, a write amplifier circuit, a plurality of input/output pins and a plurality of address pins. The write amplifier circuit is coupled to the memory bank through a plurality of internal input/output lines. The plurality of input/output pins are coupled to the write amplifier circuit through a plurality of input lines. A part of plurality of address pins receive a column address instruction, and at least one of another part of the plurality of address pins receive an operation code. The semiconductor memory determines a part of the internal input/output lines for transmitting input data according to the operation code, and operates the write amplifier circuit to perform a partial writing mode according to the operation code so as to write the input data into the memory bank according to the column address instruction.

Abstract: A memory, a memory chip and a memory data access method are provided. The memory of the disclosure includes a plurality of memory chips. Each of the plurality of memory chips includes a first bank group, a second bank group and a read amplifier and a write amplifier. The first bank group includes a plurality of first memory banks. The second bank group includes a plurality of second memory banks. The read amplifier and the write amplifier are separately coupled to the first bank group and the second bank group. The read amplifier and the write amplifier are configured to independently access different bank groups.

Abstract: A memory, a memory chip and a memory data access method are provided. The memory of the disclosure includes a plurality of memory chips. Each of the plurality of memory chips includes a first bank group, a second bank group and a read amplifier and a write amplifier. The first bank group includes a plurality of first memory banks. The second bank group includes a plurality of second memory banks. The read amplifier and the write amplifier are separately coupled to the first bank group and the second bank group. The read amplifier and the write amplifier are configured to independently access different bank groups.

Abstract: The objective of the invention is to provide a semiconductor module allowing the bandwidth between an MPU and a DRAM to be improved. This semiconductor module 1 comprises a logic chip 20, a RAM unit 40 which is a multi-layer RAM module, a spacer 60 disposed stacked over the RAM unit 40 in the layering direction thereof, an interposer 10 electrically connected to each of the logic chip 20 and the RAM unit 40, and a connection part 50 establishing a connection allowing for communication between the logic chip 20 and the RAM unit 40. The logic chip 20 and the spacer 60 are disposed to be adjacent to one another in a direction intersecting with the layering direction of the RAM unit 40, and the RAM unit 40 is placed on the interposer 10 while one end portion thereof overlaps with one end portion of the logic chip 20 in the layering direction. The connection part 50 connects the one end portion of the RAM unit 40 to the one end portion of the logic chip 20.

Abstract: A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated.

Abstract: A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated.

Abstract: A semiconductor device includes a memory cell, a bit line coupled to the memory cell, first and second wells arranged adjacently to each other, the first and second wells being different in conductivity type from each other and defining a boundary therebetween, first and second transistors formed in the first and second wells, respectively, and being different in channel type from each other, gate electrodes of the first and second transistors being connected in common to the bit line, and a third transistor formed in the first well such that the third transistor is sandwiched between the boundary and the first transistor, and a gate of the third transistor being supplied with a bit line precharge signal.

Abstract: A semiconductor device includes a memory cell, a bit line coupled to the memory cell, first and second wells arranged adjacently to each other, the first and second wells being different in conductivity type from each other and defining a boundary therebetween, first and second transistors formed in the first and second wells, respectively, and being different in channel type from each other, gate electrodes of the first and second transistors being connected in common to the bit line, and a third transistor formed in the first well such that the third transistor is sandwiched between the boundary and the first transistor, and a gate of the third transistor being supplied with a bit line precharge signal.

Abstract: A semiconductor device includes a plurality of memory cells and a sense amplifier circuit which further includes a plurality of elements such as MOS transistor formed in a well, wherein sensitive element, which are sensitive to dispersion of an impurity density in the well, is distanced from a boundary and are disposed in the center region of the well, while non-sensitive element is disposed in the peripheral region close to the boundary in the well. Since sensitive element requiring precise control of threshold voltage is disposed in the center region having uniform impurity density, and non-sensitive element allowing for less precise control of threshold voltage is disposed in the peripheral region suffering from uneven impurity density, it is possible to effectively use the overall area of the well and to thereby suppress an increase in the layout area of chips.

Abstract: Disclosed is a circuit for deciding whether or not a plural number of redundancy ROM circuits have been programmed in a preset order, with regards to addresses. In at least one of first to n-th redundancy memory circuits, an address to be substituted by a redundant address is recorded and a redundancy selection signal is output when an access address is coincident with the programmed address. It is presupposed that repair addresses are programmed from the first to the n-th redundancy ROM circuits in an ascending order with regards to address. If it is detected under this condition that a redundancy selection signal has been output from the i+1'st redundancy memory circuit while no redundancy selection signal is being output from the i-th redundancy memory circuit, an SR flip-flop is set and the sequence of the substitution decision outputs is decided to be a reversed sequence.

Abstract: There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.

Abstract: A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated.

Abstract: A semiconductor memory device with low power consumption and improved transfer rate of an input/output buffer at reduced manufacturing cost is provided. Thick-film transistors are used for a memory cell array 33, a row decoder 30, and a sense amplifier 32, surrounded by a bold broken line. Thick-film transistors having a threshold voltage lower than the aforementioned transistors are used for input buffers 11 to 13 and an input/output buffer 26, surrounded by a bold line. Thin-film transistors are used for a clock generator 16, a command decoder 17, a mode register 18, a controller 20, a row address buffer and refresh counter 21, a column address buffer and burst counter 22, a data control circuit 23, a latch circuit 24, a DLL 25, and a column decoder 31.

Abstract: A semiconductor device is configured to prevent misprogramming of fuse circuits therein. The semiconductor device includes the following elements. A group of fuse element circuits 911 is configured to store a first data defining the circuit configuration. A fuse element circuit 913 is configured to store a second data representing inhibition of programming the group of fuse element circuits. A control logic circuit 140 is configured to program the first and the second data on the fuse element circuits. An AND gate circuit 914 is configured to inhibit the control logic circuit 140 from programming the group of fuse element circuits 911 on condition that the fuse element circuit 913 has been programmed.

Abstract: A semiconductor memory device includes a first refresh cycle changing circuit that changes a refresh cycle according to an auto-refresh mode, without giving influence to a refresh cycle according to a self-refresh mode, and a second refresh cycle changing circuit that changes a refresh cycle according to the self-refresh mode, without giving influence to a refresh cycle according to the auto-refresh mode. In this way, according to the present invention, the refresh cycle according to the auto-refresh mode and the refresh cycle according to the self-refresh mode can be controlled independently. Therefore, refresh operation considering the characteristic of each mode can be executed.

Abstract: A semiconductor device includes a plurality of memory cells and a sense amplifier circuit which further includes a plurality of elements such as MOS transistor formed in a well, wherein sensitive element, which are sensitive to dispersion of an impurity density in the well, is distanced from a boundary and are disposed in the center region of the well, while non-sensitive element is disposed in the peripheral region close to the boundary in the well. Since sensitive element requiring precise control of threshold voltage is disposed in the center region having uniform impurity density, and non-sensitive element allowing for less precise control of threshold voltage is disposed in the peripheral region suffering from uneven impurity density, it is possible to effectively use the overall area of the well and to thereby suppress an increase in the layout area of chips.

Abstract: Double refresh executing means is changed in accordance with a manner (distributed refresh or burst refresh) of a refresh command so as to suppress a drop of internal power supply that occurs upon double refresh.

Abstract: A semiconductor memory device with low power consumption and improved transfer rate of an input/output buffer at reduced manufacturing cost is provided. Thick-film transistors are used for a memory cell array 33, a row decoder 30, and a sense amplifier 32, surrounded by a bold broken line. Thick-film transistors having a threshold voltage lower than the aforementioned transistors are used for input buffers 11 to 13 and an input/output buffer 26, surrounded by a bold line. Thin-film transistors are used for a clock generator 16, a command decoder 17, a mode register 18, a controller 20, a row address buffer and refresh counter 21, a column address buffer and burst counter 22, a data control circuit 23, a latch circuit 24, a DLL 25, and a column decoder 31. (FIG.

Abstract: A semiconductor memory device includes first and second bus regions, a third bus region laid out along a center line, a first cell region laid out between a first side and the first bus region, a second cell region laid out between a second side and the second bus region, third and fourth cell regions laid out between the first and second bus regions and laid out toward a third side and a fourth side respectively seen from the third bus region, and a data input/output pad string laid out along the third bus region.

Abstract: In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired. The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.