Abstract: In a method of testing a semiconductor memory device having a pipeline structure, a same data is stored in a plurality of memory cells in advance. The stored data are read out from the plurality of memory cells to produce data signals and amplified as the data signals. A determining section determines whether all the data signals are same, to generate a determination result signal. In accordance with the determination result signal, one of signals associated with the amplified data signals and predetermined signals are transferred to an output section in synchronous with a synchronous signal. The output section includes a plurality of output circuits each of which provides, as an indication signal, one of a low level signal, a high level signal and a signal indicative of a high impedance state in response to each of the transferred signals. Therefore, using at least one of the indication signals, whether the plurality of memory cells are correctly operable can be tested.

Abstract: A semiconductor pipeline memory device has a controller for producing first, second and third timing clock signals for transferring a column address and a read-out data bit through first, second and third pipeline stages to an input-and-output pin, and long time interval between two of the first, second and third timing clock signals and short time interval between another two of the first, second and third timing clock signals are respectively assigned to one of the first to third pipeline stages with relatively long signal path and another of the first to third pipeline stages with relatively short signal path, thereby decreasing undesirable time loss.

Abstract: In the semiconductor integrated circuit of the present invention, write and read operation are successively implemented in which a manner that read addresses are inputted after write addresses are inputted and read data is read from a sense amplifier starting from the next cycle after all the data have been written to the sense amplifier.

Abstract: A roll call circuit for a semiconductor memory having a plurality of redundant memory cells, comprises a circuit for cutting off a path for transferring a memory cell information to an output pad at the time of a roll call test, and another circuit for transferring the result of the roll call test to the path so that the result of the roll call test is outputted from the output pad at the time of the roll call test.

Abstract: A semiconductor memory, particularly a sychronous DRAM which includes a bus driving circuit driving read/write buses to first and second potentials in a write operation, a data amplifier driving the read/write buses to third and fourth potentials in a read operation, and a precharge control circuit precharging the data read/write buses to a precharge level to a predetermined level after the write operation has completed.

Abstract: A dynamic random access memory device internally carries out inspection sequences in a diagnostic mode of operation, and an instruction circuit incorporated therein discriminates a Write-CAS-Before-RAS entry cycle for simultaneously supplying test enable signals indicative of inspection sequences to internal test circuits, wherein the instruction circuit firstly decodes a multi-bit instruction signal and repeatedly produces a latch control signal for sequentially storing the decoded signal so that a plurality of test enable signal are simultaneously supplied to the test circuits.

Abstract: In a semiconductor memory device having first and second main data amplifiers (27, 28) for electrically charging a plurality of read bus pairs (23, 24), a precharge control circuit (26) controls operation of first and second main data amplifiers so that selected ones of the read bus pairs are electrically charged during a predetermined burst period except when each of the first and the second main data amplifiers produces a difference signal. When each of the read bus pairs has a read bus potential difference, each of the first and the second main data amplifiers produces the difference signal and electrically charges each of the read bus pairs in accordance with the difference signal. The read bus potential difference is produced dependent on a bit line potential difference which is produced in each of bit line pairs.

Abstract: A semiconductor integrated circuit device produces an internal step-down power voltage from an external voltage for selectively distributing the internal step-down power voltage and the external voltage to the circuit components thereof, and a built-in step-down voltage generator has two internal voltage generating circuits selectively enabled with a control signal for a standard data access mode and a burn-in test operation, wherein a premonitoring circuit activates a current mirror circuit for producing the control signal when the external voltage becomes close to an accelerating voltage range for the burn-in test operation, thereby decreasing standby current in the standard data access mode.

Abstract: A semiconductor integrated circuit protected against a high voltage testing signal is provided. The integrated circuit includes a first-stage input circuit, a discriminating circuit, a power suppuly circuit and a connecting circuit. The input ends of the-input circuit and the discriminating circuit are connected to one preselected external terminal. The discriminating circuit renders a testing circuit drive signal active to activate when a testing instruction signal higher than an ordinary input signal voltage is applied to the external terminal. When the testing circuit drive signal is active, the power supply circuit disconnects at least one of the positive and negative poles of the power source having polarity opposite to that of the testing instruction signal from the input circuit, and the connecting circuit connects one of the positive and negative poles of the power source having the same polarity as that of the testing instruction signal to the output end of the input circuit.

Abstract: A reference potential generating circuit includes a plurality of MOS field effect transistors and a reference potential driver circuit. The MOS field effect transistors have different threshold voltages and a reference potential is obtained by amplifying the threshold voltage difference of the MOS field effect transistors. During the period in which a power supply potential externally supplied is lower than a predetermined target value of the reference potential, the reference potential driver circuit drives an output terminal for producing a potential corresponding to the power supply potential supplied externally. In this reference potential generating circuit, the S/N ratio is good and the circuit operation is stable, and is effective for reducing the power consumption and for increasing the integration density in semiconductor integrated circuit devices.

Abstract: A dynamic random access memory device negatively biases the semiconductor substrate, and a substrate bias system incorporated therein produces a negative bias voltage from an external power voltage level for accelerating the negative biassing operation before an internal power voltage is sufficiently developed by an internal step-down circuit incorporated therein; however, after the development, the substrate bias system produces the negative bias voltage from the internal power voltage so as to be less affectable by fluctuation of the external power voltage level.

Abstract: A semiconductor integrated circuit device is equipped with an internal power source unit for distributing an internal power voltage level between component circuitries, and the internal power voltage level is regulated to a variable reference voltage level, wherein a first main voltage regulator regulates the variable reference voltage level to a primary reference voltage level before reaching a threshold voltage level; however, after the primary reference voltage level becomes lower than the threshold voltage level, a latching circuit supplies an activation signal to a second main voltage regulator, and the second main voltage regulator regulates the variable reference voltage level to a secondary reference voltage level so that the second main voltage regulator continuously controls the variable voltage level without any abrupt transition, thereby allowing the internal power source unit to adjust the internal power voltage level to an arbitrary point.

Abstract: An output gate according to the present invention includes a CMOS gate composed of a P-MOS transistor connected at a source to an external power supply and a first N-MOS transistor connected at a source to ground, and a second N-MOS transistor connected between ground and the first N-MOS transistor by a source-drain path. The second N-MOS transistor is connected at a gate to an external power supply.

Abstract: A power-on detecting circuit produces a power-on signal upon power-on event for initializing internal component circuits, and comprises a timing generating unit for producing a timing signal when a power voltage level reaches a predetermined voltage level, a monitoring unit for producing an enable signal when a step-down power voltage level reaches a constant level, and a signal generating unit for producing the power-on signal in the concurrent presence of the enable signal and the timing signal, thereby guaranteeing the initialization of the internal component circuits.

Abstract: An internal step-down circuit is incorporated in an integrated circuit device for reduction in power consumption as well as for scaling-down, and produces an internal step-down power voltage level regulated to a reference voltage level internally produced by an internal reference signal generator, wherein a diagnostic circuit compares the reference voltage level with an external variable voltage level to see if or not the reference voltage level is higher than the external voltage level, and the external variable voltage level is changed to determine the matching point therebetween, thereby confirming the reference voltage level after packaging.

Abstract: A semiconductor integrated circuit which comprises a detection circuit for detecting a voltage of a semiconductor substrate and a negative voltage generating circuit for generating a negative voltage to be supplied to the substrate in accordance with an output signal of the detection circuit. The detection circuit includes a first P-channel MOS transistor having a gate connected to a ground potential, a source connected to a power source and a drain connected to a node coupled to the detection circuit, and a second P-channel MOS transistor having a gate connected to the substrate, a source connected to the node and a drain connected to ground. Current does not flow from the external power source to the substrate, so that, even if the negative voltage generating circuit does not have its electric current supplying capacity increased, the voltage of the substrate can be detected.