Abstract: A semiconductor memory device is designed to speed up the selection of a word line.

Abstract: A semiconductor memory device is designed to speed up the selection of a word line.

Abstract: A semiconductor storage device such as a DRAM is configured to enable testing on defectiveness of memory cells by an existing memory tester, which locates defect cells to be replaced with redundancy cells by a redundancy circuit. Herein, a write circuit writes multiple-bit data to memory cells of a memory cell array under testing. Then, the multiple-bit data are read from the memory cell array by a read circuit and are compared with original one to make decisions of “pass” or “fail” on the memory cells by the memory tester. Specifically, the read circuit is configured by plural pairs of a data output circuit and a data compression circuit with respect to plural sets of prescribed data each of which consists of a prescribed number of bits corresponding to prescribed memory cells which are subjected to simultaneous replacement.

Abstract: A semiconductor memory device according to the invention comprises a first memory cell region, a second memory cell region, and a sense-amplifier row region disposed between the first and second memory cell regions, wherein the sense-amplifier row region has therein a plurality of transistor rows constituting a plurality of sense-amplifiers, at least one power-supply side sense-amplifier driver transistor disposed on the side f the first memory cell region of the plurality of transistor rows, and at least one ground side sense-amplifier driver transistor disposed on the side of the second memory cell region of the plurality of transistor rows.

Abstract: A semiconductor memory device is provided in which no delay in writing of data occurs due to increases in the output load of the data input circuit, and which is also compatible with various bit configurations. The device comprises a plurality of data input circuits for inputting data from an external source, and a plurality of data write circuits for writing data input from the plurality of data input circuits to a memory cell array. The data to be stored is input from an external source by selectively using the plurality of data input circuits, and then each bit to be stored is distributed to the plurality of data write circuits according to the bit configuration of the data. Of the plurality of data input circuits, data input from a specific data input circuit is distributed to one of the plurality of data write circuits via another data input circuit.

Abstract: According to one disclosed embodiment, a synchronous semiconductor storage device (100) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (100) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (122). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK′ in a test mode. The ICLK′ signal can be applied to internal circuits (124) allowing such circuits to operate at a higher speed. The ICLK′ signal is not applied to the mode register setting circuit (122), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit (122).

Abstract: In a synchronous semiconductor memory device including a memory cell array, a burst counter for generating an internal address signal in synchronization with an external clock signal and a decoder for reading out data from the memory cell array according to the internal address signal, an internal clock generation circuit generates an internal clock signal having a frequency equal to 1/2 of the frequency of the external clock signal in synchronization with the external clock signal, and a data output circuit outputs the data read out of the memory cell array in synchronization with both a rising edge and a falling edge of the internal clock signal.

Abstract: A semiconductor memory device is disclosed, in which the output timing of an operation enabling signal for activating the column decoder can be suitably determined according to the RAS access time. The semiconductor memory device comprises a memory cell array; a row decoder for decoding row address data for designating a word line; a column decoder for decoding column address data for designating a data line; and a column decoder control section for outputting an operation enabling signal for making the column decoder operable to the column decoder. The column decoder control section determines the output timing of the operation enabling signal according to a determination of whether a sufficient RAS access time is obtained.

Abstract: A semiconductor memory device includes a plurality of memory cell groups, the data for the plurality of memory cell groups being transmitted through mutually different buses, and a redundancy memory cell group common to the plurality of memory cell groups. The semiconductor memory device further includes a control circuit for transmitting data for one or more memory cells of the redundancy memory cell group in place of data for one or more defective memory cells in any of the plurality of memory cell groups. Each of the plurality of memory cell groups is provided corresponding to every different input/output terminal of the memory device, or the plurality of memory cell groups are provided corresponding to a common input/output terminal of the memory device.

Abstract: A delay circuit device having first and second delay circuits arrays so constructed that an output can be taken out from an arbitrary position of a signal transmission path, discriminating circuits receiving an output from two positions which divide the first delay circuit array into three portions, and three control circuits. The first and second delay circuit arrays are so arranged that the direction of signal transmission paths are opposite to each other. An output of the first delay circuit array is connected to an input of the second delay circuit array through the control circuits in the order from the position near to an input of the first delay circuit array and in the order from the position near to an output of the second delay circuit array. A first signal is supplied to the first delay circuit array, and whether or not the first signal is propagated to the output of the two positions is respectively latched in the discriminating circuits.

Abstract: In a roll call tester, a redundancy circuit is provided which, upon predetermined normal cell addressing, activates the normal cell while rendering the redundancy cell nonactive, and, upon predetermined redundancy cell addressing, renders the normal cell nonactive while, when the roll call test signal in the test signal activation circuit is nonactive, activating the redundancy cell. This construction can realize a roll call test while eliminating the need to use a redundancy detection circuit and a signal involved in the detection thereof, and can reduce chip area.

Abstract: A synchronous semiconductor memory device has a plurality of banks each including a cell array. A sensing process of the synchronous semiconductor memory device is controlled by starting a series of operations from selection of a row address to a sensing operation in response to a first external clock pulse, and synchronizing at least one event in the series of operation with a second external clock pulse subsequent to the first external clock pulse.

Abstract: In a semiconductor memory device comprising a regular memory cell array, a regular decoder, a redundant memory cell array, and a redundant decoder, the redundant decoder comprises a plurality of redundant decoding circuits each of which is supplied with a test mode signal. The redundant decoding circuits are supplied with an address signal and a complementary address signal in different order so that at least one pair of a bit in the address signal and a corresponding bit in the complementary address signal is supplied in the reverse sequence. The redundant decoder further comprises a decode inhibit signal producing arrangement for producing a decode inhibit signal indicative of active when any one of the redundant decoding circuits produces a redundant decoded signal indicative of active.

Abstract: A synchronous-type semiconductor storage which includes a first pulse generating circuit that generates a first pulse in response to the level shifting of an external clock input from a first level to a second level; and a second pulse generating circuit that generates a second pulse in response to the level shifting of a second signal input other than the external clock input; wherein an internal synchronous signal is generated in response to both the first pulse and the second pulse.

Abstract: An internal synchronous signal generating circuit outputs the internal synchronous signals ICLK1, ICLK2. A burst counter outputs an internal column address signal IADD and the lowermost internal column address signal IY0. A first and second D-F/Fs input an output of the input buffer and drives a first write bus (WBUS) in synchronization with the ICLK1. An inverting element inputs IY0. Inverting elements input outputs of the first and second D-F/Fs and drives a second write bus (WBUS). A transistor TG1 is connected between the first WBUS and second D-F/F. The gate is connected to the output of the first inverting element. A transistor TG2 is connected between the output of the second inverting element and second D-F/F with IY0 connected to the gate. A column decoder inputs IADD and outputs a column switch YSW. Sense amplifiers input the YSW and the second WBUS. A memory cell array is connected to the sense amplifiers through a bit line.

Abstract: The invention provides a semiconductor storage device which is comparatively short in read time. A read route is formed from a first read bus pair connected to a plurality of sense amplifiers, to which a bit line pair is inputted, and inputted to a first data amplifier, a second read bus pair connected to the first data amplifier connected to the sense amplifiers, to which the bit line pair is inputted, and also to a precharge circuit and inputted to a second data amplifier, a third read bus outputted from the second data amplifier and inputted to a data output buffer, and a bus extending from the data output buffer to an output terminal. The precharge circuit is connected to the second read buses in the proximity of the first data amplifier connected to the second read buses at a position remote from the connection points between the second data amplifier and the second read buses.

Abstract: In a synchronous semiconductor memory device including a memory cell array, a burst counter for generating an internal address signal in synchronization with an external clock signal and a decoder for reading out data from the memory cell array according to the internal address signal, an internal clock generation circuit generates an internal clock signal having a frequency equal to 1/2 of the frequency of the external clock signal in synchronization with the external clock signal, and a data output circuit outputs the data read out of the memory cell array in synchronization with both a rising edge and a falling edge of the internal clock signal.

Abstract: In a synchronous semiconductor memory, there is provided a write pulse generating circuit receiving a pipeline enable signal, a write enable signal and an internal synchronous signal which is generated by delaying an output of an internal synchronous signal generating circuit by a first delay. This write pulse generating circuit includes a second delay, and is configured to generate a write pulse which is put into an inactivate condition for a constant time corresponding to a delay time of the second delay when the internal synchronous signal is brought to a high level, and thereafter, is maintained in an activate condition until the next internal synchronous signal is supplied. Thus, by adjusting the delay amount of the first delay and the delay amount of the second delay, a column selection line is never switched during a period that a write data is being supplied to write bus pairs, so that the write data is accurately written into a sense amplifier.

Abstract: A semiconductor memory device of a synchronous type is disclosed, which has an output control circuit (14) adapted to output signals D2T and D2N by activating one of two conduction control signals D1T or by inactivating both of the conduction control signals in accordance with an output control signal MSK2B or OEB for controlling whether a data output terminal DQ is to be actuated or set into a high impedance, and an output circuit 17 provided with a couple of latch circuits 15 and 16 each adapted to individually latch and output the corresponding conduction control signals in synchronism with an internal synchronizing signal .phi.3. There is further provided an additional latch circuit 13 latching the output control signal in response to an inverted signal of the internal synchronizing signal .phi.3.

Abstract: The semiconductor memory device of the present invention is provided with at least: a first sync-signal generation circuit that generates and outputs a first sync-signal synchronized with any of a first clock inputted from the outside and a second and third clock inputted after the first clock; a first delay circuit that delays the first sync-signal by a prescribed time interval and outputs the result as a second sync-signal; a first latch circuit that latches the second sync-signal; a second latch circuit that latches the first sync-signal; and a third latch circuit that detects that both the first and second latch circuits have latched the second sync-signal and the first sync-signal, respectively, and latches this detection; the output of the third latch circuit then being used to control a pipeline circuit.