Patents by Inventor Yasuko Yoshida

Yasuko Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110229980
    Abstract: The present teaching provides a fluorescent oligonucleotide probe having a high degree of design flexibility and wide applicability, as well as the use thereof. This is an oligonucleotide probe capable of forming a stem and loop, comprising at least one fluorophore located between adjacent nucleotides in the stem and is linked to a unit represented by Formula (1) and at least one quencher located at a site capable of pairing up with the at least one fluorophore located between the adjacent nucleotides in the stem and is linked to a unit represented by Formula (2). (In the formulae, X represents the fluorophore, Y represents the quencher, R1 represents an optionally substituted C2 or C3 alkylene chain, R2 represents an optionally substituted C0-2 alkylene chain, and Z represents a direct bond or linker.
    Type: Application
    Filed: December 31, 2010
    Publication date: September 22, 2011
    Applicants: National University Corporation Nagoya University, NGK Insulators, Ltd.
    Inventors: Hiroyuki ASANUMA, Xingguo Liang, Hiromu Kashida, Yasuko Yoshida, Tomokazu Takase, Kousuke Niwa
  • Publication number: 20110046015
    Abstract: Disclosed is a peptide immobilization technique which can achieve the immobilization of a satisfactory quantity of a peptide on a solid support. In the immobilization of a peptide on a solid support, a surfactant is allowed to coexist on the solid support together with the peptide. In this manner, the quantity of the peptide immobilized on the solid support can be increased.
    Type: Application
    Filed: January 29, 2009
    Publication date: February 24, 2011
    Inventors: Hiroyuki Honda, Tsutomu Kawabe, Mina Okochi, Miyoko Matsushima, Naoki Matsumoto, Mitsuo Kawase, Yasuko Yoshida, Tomokazu Takase
  • Patent number: 7893505
    Abstract: In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: February 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Nishida, Yasuko Yoshida, Shuji Ikeda
  • Patent number: 7666728
    Abstract: A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: February 23, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Shuji Matsuo, Katsuhiro Uchimura, Yasuko Yoshida, Kota Funayama, Yutaka Takeshima
  • Patent number: 7601532
    Abstract: A microarray for predicting the prognosis of neuroblastoma, wherein the microarray has 25 to 45 probes related to good prognosis, which are hybridized to a gene transcript whose expression is increased in a good prognosis patient with neuroblastoma and are selected from 96 polynucleotides consisting of the nucleotide sequences of SEQ. ID NOs. 1, 5, 6, 14. 16, 17, 19, 22-24, 28, 29, 31, 37, 39, 40, 43, 44, 47-52, 54, 57-60, 62, 64, 65, 67, 68, 72-75, 77, 78, 80-82, 84, 87, 89-91, 94, 100, 103, 112, 113, 118, 120, 129, 130, 132, 136, 138, 142, 144, 145, 148, 150-153, 155, 158-160, 163-165, 169-171, 173, 174, 177, 178, 180-182, 184, 186, 187, 189, 191, 192, 194, 195, 198-200 or their partial continuous sequences or their complementary strands, and 25 to 45 probes related to poor prognosis, which are hybridized to a gene transcript whose expression is increased in a poor prognosis patient with neuroblastoma and are selected from 104 polynucleotides consisting of the nucleotide sequences of SEQ. ID NOs.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: October 13, 2009
    Assignees: Hisamitsu Pharmaceutical Co., Inc., NGK Insulators, Ltd., Chiba-Prefecture
    Inventors: Akira Nakagawara, Miki Ohira, Shin Ishii, Takeshi Goto, Hiroyuki Kubo, Takahiro Hirata, Yasuko Yoshida, Saichi Yamada
  • Publication number: 20090218608
    Abstract: In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.
    Type: Application
    Filed: January 30, 2009
    Publication date: September 3, 2009
    Inventors: Akio NISHIDA, Yasuko Yoshida, Shuji Ikeda
  • Publication number: 20090042734
    Abstract: An object of the present invention is to provide a probe array having partitioned array regions with uniform surface chemical properties. The probe array of the present invention includes a substrate having a plurality of partitioned array regions where many probes are immobilized and a separator attached to the substrate and including partitions partitioning the array regions. The above object can be achieved by attaching the separator including the partitions capable of partitioning instead of forming hydrophobic regions on a surface of the substrate by printing or chemical treatment.
    Type: Application
    Filed: March 27, 2006
    Publication date: February 12, 2009
    Applicant: NGK INSULATORS, LTD.
    Inventors: Yasuko Yoshida, Kazunari Yamada, Tomokazu Takase, Akinobu Oribe
  • Patent number: 7488639
    Abstract: In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: February 10, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Akio Nishida, Yasuko Yoshida, Shuji Ikeda
  • Publication number: 20080287313
    Abstract: A novel chip capable of reducing a reaction period, applying wide-ranging target substance, preventing a mismatch binding efficiently and enabling a highly accurate detection is provided. Thus, an inventive reactive chip has the capture probe (60) fixed on each of three or more vibration areas (50) arranged on the support (30), the capture probes being able to binding to a target substance, wherein each vibration area has the vibration-generating part (40) having the first electrode (11) and the second electrode (12) between which the piezoelectric/electrostrictive element (20) is sandwiched.
    Type: Application
    Filed: July 16, 2008
    Publication date: November 20, 2008
    Applicant: NGK INSULATORS, LTD.
    Inventors: Yasuko Yoshida, Toshikazu Hirota, Yukihisa Takeuchi
  • Publication number: 20080268453
    Abstract: A method for determining the prognosis of a CD5+DLBCL patient and a CD5-DLBCL patient is provided. It is determined that, in the chromosomal DNA from a patient with lymphoma, (1) the prognosis of the CD5+DLBCL patient with amplification of 13q21.1-q31.3 region is poor; (2) the prognosis of the CD5+DLBCL patient with deletion of 1p36.21-p36.13 region is poor; and (3) the prognosis of the CD5-DLBCL patient with amplification of 5p15.33-p14.2 region is good.
    Type: Application
    Filed: February 6, 2008
    Publication date: October 30, 2008
    Applicants: AICHI PREFECTURE, NGK INSULATORS, LTD.
    Inventors: Masao Seto, Hiroyuki Tagawa, Yasuko Yoshida, Shigeki Kira
  • Publication number: 20080240946
    Abstract: A microchemical chip comprises a plate-shaped substrate, with a channel formed on a surface of the substrate through which a fluid flows. A fluid storage section for storing the fluid communicates with the channel at a starting end of the channel. A fluid discharge section communicates with the channel at a terminal end of the channel. An extruding pump section is formed integrally on the substrate, at a portion of the channel in the vicinity of the fluid storage section.
    Type: Application
    Filed: May 8, 2008
    Publication date: October 2, 2008
    Applicant: NGK INSULATORS, LTD.
    Inventors: Toshikazu Hirota, Yasuko Yoshida
  • Publication number: 20080200347
    Abstract: The present invention provides a hybridization method suited for using a signal probe. An array of the present invention comprises: a substrate; a nucleic acid probe that is fixed to the substrate and is hybridized with a sample to have a signal change; and at least one cavity that is filled with a specific liquid containing the sample and causing the hybridization of the nucleic acid probe with the sample. The array in this arrangement effectively enhances the reproducibility and the efficiency of hybridization with the signal probe.
    Type: Application
    Filed: January 16, 2006
    Publication date: August 21, 2008
    Applicant: NGK INSULATORS, LTD.
    Inventors: Yasuko Yoshida, Kazunari Yamada, Kousuke Niwa
  • Patent number: 7414117
    Abstract: A novel nucleotide derivative, in case of existing as a member of a single-stranded sequence, undergoing a change in the fluorescent signal intendity depending on the corresponding base type in the partner strand with which the single-stranded sequence is hybridized, and which is a thymin/uracil derivative (1) emitting light most intensely when a confronting base in the partner strand with which the single-stranded nucleotide sequence is hybridized is adenine; a cytosine derivative (2) emitting light most intensely when the confronting base is guanine; an adenine derivative (3) emitting light most intensely when the confronting base is cytosine; a guanine derivative (4) emitting light most intensely when the confronting base is cytosine or thymine/uracil; and an adrnine derivative (5) emitting light most intensely when the confronting base is thymine/uracil/.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: August 19, 2008
    Assignees: NGK Insulators, Ltd.
    Inventors: Isao Saito, Akimitsu Okamoto, Yoshio Saito, Yasuko Yoshida, Kousuke Niwa
  • Patent number: 7405346
    Abstract: This invention provides a novel gene that can impart salt stress tolerance to plants for a long period of time and salt stress tolerant transgenic plants to which such gene has been introduced. Such novel gene encodes the following protein (a), (b), or (c), and such salt stress tolerant transgenic plant has such gene introduced therein: (a) a protein consisting of the amino acid sequence as shown in SEQ ID NO: 2 in the Sequence Listing; (b) a protein consisting of an amino acid sequence derived from the amino acid sequence as shown in SEQ ID NO: 2 in the Sequence Listing by deletion, substitution, or addition of one or several amino acid residues and having activity of imparting salt stress tolerance to plants; or (c) a protein consisting of an amino acid sequence derived from the amino acid sequence as shown in SEQ ID NO: 2 in the Sequence Listing by deletion, substitution, or addition of one or several amino acid residues and having UDP-glucose 4-epimerase activity.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: July 29, 2008
    Assignees: Taisei Corporation, Ajinomoto Co., Inc.
    Inventors: Noboru Endo, Kouki Yoshida, Miho Akiyoshi, Yasuko Yoshida, Chieko Ohsumi, Daisuke Igarashi
  • Patent number: 7402473
    Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: July 22, 2008
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
  • Patent number: 7397104
    Abstract: A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: July 8, 2008
    Assignee: Elpida Memory, Inc.
    Inventors: Norio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda
  • Publication number: 20080142901
    Abstract: A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.
    Type: Application
    Filed: February 8, 2008
    Publication date: June 19, 2008
    Inventors: Shuji MATSUO, Katsuhiro Uchimura, Yasuko Yoshida, Kota Funayama, Yutaka Takeshima
  • Patent number: 7348230
    Abstract: A method of manufacture of a semiconductor device includes forming a gate insulating film and a gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: March 25, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Shuji Matsuo, Katsuhiro Uchimura, Yasuko Yoshida, Kota Funayama, Yutaka Takeshima
  • Publication number: 20080070795
    Abstract: The present invention aims to provide a technique for stably immobilizing a probe on a carrier The present invention provides a linker compound represented by formula (1): wherein A represents a hydrogen atom, another substituent, a sugar, or a derivative thereof.
    Type: Application
    Filed: September 7, 2007
    Publication date: March 20, 2008
    Applicants: KYOTO UNIVERSITY, SHINWA CHEMICAL INDUSTRIES, LTD., NGK Insulators, Ltd.
    Inventors: Keisuke Makino, Tsutomu Kodaki, Seiya Watanabe, Seung Pack, Mitsuru Nonogawa, Hiroo Wada, Yasuko Yoshida, Kazunari Yamada
  • Patent number: 7341697
    Abstract: A reaction cell is provided with a vessel-like cell main body and a circular piezoelectric/electrostrictive oscillator fixed to an outside of a bottom surface of the cell main body. The cell main body includes a circular bottom plate portion and a circumferential wall portion which rises from a circumferential edge of the bottom plate portion so as to thereby surround the bottom plate portion. The bottom plate portion and the circumferential wall portion are integrally formed from ceramics. A solution accommodation space is formed above the bottom plate portion and is partially enclosed by the circumferential wall portion. The piezoelectric/electrostrictive oscillator is concentrically adhered to the outside of the bottom surface of the cell main body.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: March 11, 2008
    Assignee: NGK Insulators, Ltd.
    Inventors: Yukihisa Takeuchi, Yasuko Yoshida, Toshikazu Hirota