Patents by Inventor Yasuko Yoshida
Yasuko Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080050285Abstract: A reaction cell is provided with a vessel-like cell main body and a circular piezoelectric/electrostrictive oscillator fixed to an outside of a bottom surface of the cell main body. The cell main body includes a circular bottom plate portion and a circumferential wall portion which rises from a circumferential edge of the bottom plate portion so as to thereby surround the bottom plate portion. The bottom plate portion and the circumferential wall portion are integrally formed from ceramics. A solution accommodation space is formed above the bottom plate portion and is partially enclosed by the circumferential wall portion. The piezoelectric/electrostrictive oscillator is concentrically adhered to the outside of the bottom surface of the cell main body.Type: ApplicationFiled: October 24, 2007Publication date: February 28, 2008Applicant: NGK Insulators, Ltd.Inventors: Yukihisa TAKEUCHI, Yasuko Yoshida, Toshikazu Hirota
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Patent number: 7323555Abstract: A novel nucleotide derivative, in case of existing as a member of a single-stranded sequence, undergoing a change in the fluorescent signal intensity depending on the corresponding base type in the partner strand with which the single-stranded sequence is hybridized, and which is (1) a thymine/uracil derivative emitting light most intensely when a confronting base in the partner strand with which the single-stranded nucleotide sequence is hybridized is adenine; (2) a cytosine derivative emitting light most intensely when the confronting base is guanine; (3) an adenine derivative emitting light most intensely when the confronting base is cytosine; and, (4) a guanine derivative emitting light most intensely when the confronting base is cytosine or thymine/uracil.Type: GrantFiled: December 24, 2003Date of Patent: January 29, 2008Assignees: Isao Saito, NGK Insulators, Ltd.Inventors: Isao Saito, Akimitsu Okamoto, Yasuko Yoshida
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Publication number: 20080004208Abstract: In order to more accurately analyze a change in the complicated gene copy number in malignant lymphoma and identify a region affected by an important genomic aberration in greater detail so that the results can be used in diagnosing the type of disease and performing prognosis, genome-wide array CGH is carried out and thus human chromosome 136.23 to p36.32, human chromosome 1 q42.2 to q43, human chromosome 2 p11.2, human chromosome 2 q13, human chromosome 17 p11.2 to p13.3, and human chromosome 19 p13.2 to p13.3 are identified.Type: ApplicationFiled: December 5, 2005Publication date: January 3, 2008Applicants: AICHI PREFECTURE, NGK INSULATORS, LTD.Inventors: Masao Seto, Hiroyuki Tagawa, Yasuko Yoshida, Shigeki Kira
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Publication number: 20070292853Abstract: A DNA array for detecting a single nucleotide polymorphism of a gene, which comprises, on a solid support, a first probe spots group consisting of one or more probe spots each containing one or more probes hybridizable with a polynucleotide of the gene, in which the probes are exactly complementary to the first polymorphism pattern of the gene, and a second probe spots group consisting of one or more probe spots each containing one or more probes hybridizable with the polynucleotide of the gene, in which the probes are exactly complementary to the second polymorphism pattern of the gene, wherein probe lengths in the probe spots is different from each other. This DNA array enables more exact SNP detection.Type: ApplicationFiled: March 18, 2005Publication date: December 20, 2007Applicants: TOYOBO CO., LTD., NGK INSULATORS, LTD.Inventors: Mitsuo Kawase, Yasuko Yoshida, Kazunari Yamada, Yutaka Takarada, Kouzo Hashimoto
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Publication number: 20070238870Abstract: The hybridization device of the invention aims to attain a hybridization reaction of high reproducibility. A hybridization device 2 for a hybridization reaction of nucleic acid has a cover member 10 that defines a cavity 12, which includes a nucleic acid fixation area 6 of a substrate 4 for fixation of a nucleic acid probe and has capacity for storage of a liquid for the hybridization reaction therein. At least part of an area exposed to inside of the cavity 12 forms a hydrophobic region 18. Adequate control of the surface characteristic of the area exposed to the cavity for implementing the hybridization reaction desirably enhances the signal intensity and reduces a variation in signal intensity, thus attaining the hybridization reaction of high reproducibility.Type: ApplicationFiled: July 29, 2005Publication date: October 11, 2007Applicant: NGK Insulators, Ltd.Inventors: Mitsuo Kawase, Yasuko Yoshida, Kazunari Yamada, Tomokazu Takase
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Patent number: 7200254Abstract: Technology is disclosed for highly accurate automated execution of processing for alignment of a detection area to a DNA microarray image file and processing for quantitative determination of success/failure of the alignment during DNA microarray analysis. A probe reactive chip used for the technology comprises a substrate; a spot region wherein spots for fixing a probe capable of specifically reacting to a sample marked so as to be optically detectable are formed in a matrix on a surface of the substrate; and a reference pattern area, which is arranged within the spot region or approximate to the spot region, and comprises a plurality of different alignment marks in order to correct misalignment of the spot during analysis of the sample on the surface of the substrate.Type: GrantFiled: September 5, 2002Date of Patent: April 3, 2007Assignee: NGK Insulators, Ltd.Inventors: Shigeki Kira, Kazunari Yamada, Toshikazu Hirota, Yasuko Yoshida
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Publication number: 20070028332Abstract: This invention provides a novel gene that can impart salt stress tolerance to plants for a long period of time and salt stress tolerant transgenic plants to which such gene has been introduced. Such novel gene encodes the following protein (a), (b), or (c), and such salt stress tolerant transgenic plant has such gene introduced therein: (a) a protein consisting of the amino acid sequence as shown in SEQ ID NO: 2 in the Sequence Listing; (b) a protein consisting of an amino acid sequence derived from the amino acid sequence as shown in SEQ ID NO: 2 in the Sequence Listing by deletion, substitution, or addition of one or several amino acid residues and having activity of imparting salt stress tolerance to plants; or (c) a protein consisting of an amino acid sequence derived from the amino acid sequence as shown in SEQ ID NO: 2 in the Sequence Listing by deletion, substitution, or addition of one or several amino acid residues and having UDP-glucose 4-epimerase activity.Type: ApplicationFiled: April 15, 2004Publication date: February 1, 2007Applicants: TAISEI CORPORATION, AJINOMOTO CO., INC.Inventors: Noboru Endo, Kouki Yoshida, Miho Akiyoshi, Yasuko Yoshida, Chieko Ohsumi, Daisuke Igarashi
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Patent number: 7088001Abstract: In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.Type: GrantFiled: May 13, 2004Date of Patent: August 8, 2006Assignees: Hitachi, Ltd., Hitachi Ulsi Systems Co., Ltd.Inventors: Hiroshi Ashihara, Tatsuyuki Saito, Uitsu Tanaka, Hidenori Suzuki, Hideaki Tsugane, Yasuko Yoshida, Ken Okutani
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Patent number: 7067864Abstract: In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.Type: GrantFiled: December 26, 2001Date of Patent: June 27, 2006Assignee: Renesas Technology Corp.Inventors: Akio Nishida, Yasuko Yoshida, Shuji Ikeda
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Publication number: 20060128094Abstract: In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.Type: ApplicationFiled: January 31, 2006Publication date: June 15, 2006Inventors: Akio Nishida, Yasuko Yoshida, Shuji Ikeda
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Patent number: 7045864Abstract: A semiconductor integrated circuit device, e.g., a memory cell of an SRAM, is formed of a pair of inverters having their input and output points connected in a crisscross manner and being formed of drive n-channel MISFETs and load p-channel MISFETs. The n-channel MISFETs and p-channel MISFETs have their back gates supplied with power supply voltage and a ground voltage, respectively. The MISFETs are formed with a metal silicide layer on the gate electrodes G and source regions (hatched areas) and without the formation of a metal silicide layer on the drain regions, respectively, whereby the leakage current of the MISFETs due to a voltage difference between the drain regions and wells can be reduced, and, thus, the power consumption can be reduced.Type: GrantFiled: June 14, 2002Date of Patent: May 16, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Kota Funayama, Yasuko Yoshida, Masaru Nakamichi, Akio Nishida
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Publication number: 20050287541Abstract: A microarray for predicting the prognosis of neuroblastoma, wherein the microarray has 25 to 45 probes related to good prognosis, which are hybridized to a gene transcript whose expression is increased in a good prognosis patient with neuroblastoma and are selected from 96 polynucleotides consisting of the nucleotide sequences of Seq. ID No. 1 to 96 or their partial continuous sequences or their complementary strands, and 25 to 45 probes related to poor prognosis, which are hybridized to a gene transcript whose expression is increased in a poor prognosis patient with neuroblastoma and are selected from 104 polynucleotides consisting of the nucleotide sequences of Seq. ID No. 97 to 200 or their partial continuous sequences or their complementary strands.Type: ApplicationFiled: September 23, 2004Publication date: December 29, 2005Applicants: Hisamitsu Pharmaceutical Co., Inc., NGK Insulators, Ltd., Chiba-PrefectureInventors: Akira Nakagawara, Miki Ohira, Shin Ishii, Takeshi Goto, Hiroyuki Kubo, Takahiro Hirata, Yasuko Yoshida, Saichi Yamada
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Publication number: 20050282177Abstract: A method for determining the prognosis of a CD5+DLBCL patient and a CD5?DLBCL patient is provided. It is determined that, in the chromosomal DNA from a patient with lymphoma, (1) the prognosis of the CD5+DLBCL patient with amplification of 13q21.1-q31.3 region is poor; (2) the prognosis of the CD5+DLBCL patient with deletion of 1p36.21-p36.13 region is poor; and (3) the prognosis of the CD5?DLBCL patient with amplification of 5p15.33-p14.2 region is good.Type: ApplicationFiled: September 22, 2004Publication date: December 22, 2005Applicants: AICHI PREFECTURE, NGK INSULATORS, LTD.Inventors: Masao Seto, Hiroyuki Tagawa, Yasuko Yoshida, Shigeki Kira
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Publication number: 20050196935Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: ApplicationFiled: April 19, 2005Publication date: September 8, 2005Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Publication number: 20050145897Abstract: A method of manufacture of a semiconductor device includes forming a gate insulating film and a gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.Type: ApplicationFiled: December 10, 2004Publication date: July 7, 2005Inventors: Shuji Matsuo, Katsuhiro Uchimura, Yasuko Yoshida, Kota Funayama, Yutaka Takeshima
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Patent number: 6897499Abstract: A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end thereof to the other end thereof. The gate electrode has a gate length in a boundary region defined between the active region and the element isolation trench which is greater than a gate length in a central portion of the active region. The gate electrode is configured in an H-type flat pattern. Further, the gate electrode covers the whole of one side extending along a gate-length direction, of the boundary region defined between the active region L and the element isolation trench, and parts of two sides thereof extending along a gate-width direction. The MISFETs are formed in electrically separated wells and are connected in series to constitute part of a reference voltage generating circuit.Type: GrantFiled: February 7, 2003Date of Patent: May 24, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Akio Nishida, Noriyuki Yabuoshi, Yasuko Yoshida, Kazuhiro Komori, Sousuke Tsuji, Hideo Miwa, Mitsuhiro Higuchi, Koichi Imato
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Patent number: 6881646Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: GrantFiled: March 21, 2003Date of Patent: April 19, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Publication number: 20050059037Abstract: A novel nucleotide derivative, in case of existing as a member of a single-stranded sequence, undergoing a change in the fluorescent signal intensity depending on the corresponding base type in the partner strand with which the single-stranded sequence is hybridized, and which is a thymine/uracil derivative (1) emitting light most intensely when a confronting base in the partner strand with which the single-stranded nucleotide sequence is hybridized is adenine; a cytosine derivative (2) emitting light most intensely when the confronting base is guanine; an adenine derivative (3) emitting light most intensely when the confronting base is cytosine; a guanine derivative (4) emitting light most intensely when the confronting base is cytosine or thymine/uracil; and an adenine derivative (5) emitting light most intensely when the confronting base is thymine/uracil.Type: ApplicationFiled: March 9, 2004Publication date: March 17, 2005Applicants: ISAO SAITO, NGK INSULATORS, LTD.Inventors: Isao Saito, Akimitsu Okamoto, Yoshio Saito, Yasuko Yoshida, Kousuke Niwa
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Publication number: 20050053484Abstract: A microchemical chip (10A) comprises a plate-shaped substrate (12), with a channel (14) formed on a surface of the substrate (12) through which a fluid flows. A fluid storage section (16) for storing the fluid communicates with the channel (14) at a starting end of the channel (14). A fluid discharge section (18) communicates with the channel (14) at a terminal end of the channel (14). An extruding pump section (22) is formed integrally on the substrate (12), at a portion of the channel (14) in the vicinity of the fluid storage section (16).Type: ApplicationFiled: February 18, 2003Publication date: March 10, 2005Applicant: NGK INSULATORS, LTDInventors: Toshikazu Hirota, Yasuko Yoshida
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Patent number: 6858515Abstract: A semiconductor device free from electric failure in transistors at upper trench edges can be produced by a simplified process comprising basic steps of forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation presention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film, etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; oxidizing the trench formed in the semiconductor substrate; embedding an embedding isolation film in the oxidized trench; removing the embedding isolation film formed on the oxidation prevention film; removing the oxidation prevention film formed on the circuit-forming side of the semiconductor substrate; and removing the pad oxiType: GrantFiled: August 12, 2003Date of Patent: February 22, 2005Assignee: Renesas Technology Corp.Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Yasuko Yoshida, Norio Suzuki, Kozo Watanabe, Kenji Kanamitsu