Abstract: A probe solution composition containing a probe capable of binding specifically to a target substance and a moisturizer, which is utilized for spotting the probe to be fixed on a substrate, is provided. As a result, an increased detection sensitivity of a reaction chip, a higher spot shape stability and a simplified manufacturing process can be achieved.

Abstract: A protection film is formed on a silicon oxide film 6 formed on the surface of a semiconductor substrate, a silicon oxide film is removed from a region where a thin gate-insulating film is to be formed by using, as a mask, a photoresist pattern that covers a region where a thick gate-insulating film is to be formed, and, then, the photoresist pattern is removed followed by washing. Then, the semiconductor substrate is heat-oxidized or a film is deposited thereon to form gate-insulating films having different thicknesses.

Abstract: In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.

Abstract: A novel chip capable of reducing a reaction period, applying wide-ranging target substance, preventing a mismatch binding efficiently and enabling a highly accurate detection is provided. Thus, an inventive reactive chip has the capture probe (60) fixed on each of three or more vibration areas (50) arranged on the support (30), the capture probes being able to binding to a target substance, wherein each vibration area has the vibration-generating part (40) having the first electrode (11) and the second electrode (12) between which the piezoelectric/electrostrictive element (20) is sandwiched.

Abstract: An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

Abstract: A novel nucleotide derivative, in case of existing as a member of a single-stranded sequence, undergoing a change in the fluorescent signal intensity depending on the corresponding base type in the partner strand with which the single-stranded sequence is hybridized, and which is (1) a thymine/uracil derivative emitting light most intensely when a confronting base in the partner strand with which the single-stranded nucleotide sequence is hybridized is adenine; (2) a cytosine derivative emitting light most intensely when the confronting base is guanine; (3) an adenine derivative emitting light most intensely when the confronting base is cytosine; and, (4) a guanine derivative emitting light most intensely when the confronting base is cytosine or thymine/uracil.

Abstract: A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.

Abstract: In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.

Abstract: An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

Abstract: A semiconductor device free from electric failure in transistors at upper trench edges can be produced by a simplified process comprising basic steps of forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation presention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film, etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; oxidizing the trench formed in the semiconductor substrate; embedding an embedding isolation film in the oxidized trench; removing the embedding isolation film formed on the oxidation prevention film; removing the oxidation prevention film formed on the circuit-forming side of the semiconductor substrate; and removing the pad oxi

Abstract: Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

Abstract: A protection film is formed on a silicon oxide film 6 formed on the surface of a semiconductor substrate, a silicon oxide film is removed from a region where a thin gate-insulating film is to be formed by using, as a mask, a photoresist pattern that covers a region where a thick gate-insulating film is to be formed, and, then, the photoresist pattern is removed followed by washing. Then, the semiconductor substrate is heat-oxidized or a film is deposited thereon to form gate-insulating films having different thicknesses.

Abstract: In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode, and a soft error produced due to an &agr; ray can be reduced. Since a capacitance can be formed even at each sidewall of the wiring, an increase in capacity can be achieved.

Abstract: A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.

Abstract: A reaction cell 1 is provided with a vessel-like cell main body 2 and a circular piezoelectric/electrostrictive oscillator 3 fixed to an outside of a bottom surface of the cell main body 2. The cell main body 2 is composed of a circular bottom plate portion 2A and a circumference wall portion 2B which rises from a circumferential edge of the bottom plate portion 2A so as to thereby surround the bottom plate portion 2A. The bottom plate portion 2A and the circumferential wall portion 2B are made of ceramics and integrally formed. A space formed above the bottom plate portion 2A and surrounded by the circumferential wall portion 2B is a solution accommodation space 4. The piezoelectric/electrostrictive oscillator 3 is concentrically adhered to the outside of the bottom surface of the cell main body 3.

Abstract: A semiconductor device and process of forming the device are described. The process includes forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation prevention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film; etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; and oxidizing the trench formed in the semiconductor substrate. The produced device has round upper trench edges obtained by conducting isotropic etching of the exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.

Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Abstract: Technology is disclosed for highly accurate automated execution of processing for alignment of a detection area to a DNA microarray image file and processing for quantitative determination of success/failure of the alignment during DNA microarray analysis. A probe reactive chip used for the technology comprises a substrate; a spot area wherein spots for fixing a probe capable of specifically reacting to a sample marked so as to be optically detectable are formed in a matrix on a surface of the substrate; and a reference pattern area, which is arranged within the spot area or approximate to the spot area, and comprises a plurality of different alignment marks in order to correct misalignment of the spot during analysis of the sample on the surface of the substrate.

Abstract: An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

Abstract: Technology is disclosed for highly accurate automated execution of processing for alignment of a detection area to a DNA microarray image file and processing for quantitative determination of success/failure of the alignment during DNA microarray analysis. A probe reactive chip used for the technology comprises a substrate; a spot region wherein spots for fixing a probe capable of specifically reacting to a sample marked so as to be optically detectable are formed in a matrix on a surface of the substrate; and a reference pattern area, which is arranged within the spot region or approximate to the spot region, and comprises a plurality of different alignment marks in order to correct misalignment of the spot during analysis of the sample on the surface of the substrate.