Patents by Inventor Yasuo Kobayashi

Yasuo Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9177846
    Abstract: Provided is a holding stage structure which holds a substrate and disposed in a process chamber that is vacuum-evacuatable and allows a predetermined process to be performed on the substrate therein. The holding stage structure includes: a holding stage body on which the substrate is placed; an elevation pin mechanism lowering the substrate on the holding stage body or raising the substrate from the holding stage body; and a stepped portion formed on the holding stage body so that a peripheral portion of a rear surface of the substrate placed on the holding stage body is exposed to a processing gas supplied into the process chamber.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: November 3, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kohei Kawamura, Yasuo Kobayashi, Toshihisa Nozawa, Kiyotaka Ishibashi
  • Publication number: 20150255258
    Abstract: Provided is a plasma processing apparatus including: a rotary mounting table supported by a rotatory shaft arranged rotatably within a processing chamber and including multiple substrate placement units arranged side by side in a circumferential direction; a processing gas supplying section for supplying processing gas into the processing chamber; a plasma generating section wherein multiple microwave introducing mechanisms, each provided on the ceiling of the processing chamber so as to face the rotary mounting table and used for generating a plasma of the processing gas, are arranged in multiple rows spaced apart from each other from the inside of the movement path of the substrates when the rotary mounting table is rotated to the outside, each row of microwave introducing mechanisms being formed by arranging the microwave introducing mechanisms annularly side by side along the circumferential direction; and an exhaust unit that evacuates an inside of the processing chamber.
    Type: Application
    Filed: June 18, 2013
    Publication date: September 10, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Toshihisa Nozawa, Masahide Iwasaki, Takenao Nemoto, Yasuo Kobayashi, Takehisa Saito
  • Publication number: 20150155141
    Abstract: A plasma processing apparatus of the present disclosure includes a processing container provided with an opening to carry an object to be processed (“workpiece”) into or out of a chamber adjacent to the processing container; a microwave introducing mechanism configured to introduce microwaves into the processing container; an exhaust device configured to evacuate the processing container; and a thermal insulating member provided between an outer surface of a gate valve that is provided near the opening and the chamber adjacent to the processing container. The thermal insulating member is coated with a conductive film at least on a surface of the thermal insulating member facing the outer surface of the gate valve, a surface of the thermal insulating member facing the chamber adjacent to the processing container, and a surface of the thermal insulating member exposed to outer air.
    Type: Application
    Filed: December 2, 2014
    Publication date: June 4, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yasuo KOBAYASHI, Masahide IWASAKI, Koji YAMAGISHI
  • Patent number: 8765605
    Abstract: A method for manufacturing semiconductor devices includes the steps of annealing an insulating layer and forming a barrier layer including a metal element over the insulating layer. The insulating layer includes a fluorocarbon (CFx) film. The barrier layer is formed by a high-temperature sputtering process after the annealing step.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: July 1, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Masahiro Horigome, Takuya Kurotori, Yasuo Kobayashi, Takaaki Matsuoka, Toshihisa Nozawa
  • Patent number: 8503214
    Abstract: A semiconductor memory device provided with a new bit line hierarchization method that enables further reduction of power consumption is provided. The semiconductor memory device includes multiple memory blocks provided in a matrix configuration and multiple main bit lines provided in correspondence with the memory blocks. Each of the memory blocks includes: multiple memory cells provided in a matrix configuration; multiple sub bit lines provided on a column-by-column basis; multiple word lines provided with respect to each of columns and rows and common to multiple memory blocks; and a switch circuit that couples a corresponding main bit line to any of the sub bit lines. In the operation of reading a target cell as the target of read, a main bit line corresponding to the target cell is selected, a sub bit line corresponding to the column of the target cell is selected through the switch circuit; and a word line corresponding to the column and the row of the target cell is selected from among the word lines.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: August 6, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Yasuo Kobayashi
  • Publication number: 20130130513
    Abstract: The interlayer insulating layer forming method for forming an interlayer insulating layer of a semiconductor device via a plasma CVD method includes: carrying a substrate into a depressurized processing container; supplying a plasma generating gas to a first space spaced apart from the substrate; exciting the plasma generating gas in the first space; and supplying a raw material gas including a boron compound that includes at least a hydrogen group or hydrocarbon group, to a second space between the first space and the substrate. Also, a semiconductor device is interconnected in a multilayer through an interlayer insulating layer having an amorphous structure including boron, carbon, and nitrogen, wherein, in the interlayer insulating layer, a hydrocarbon group or an alkyl amino group is mixed in the amorphous structure comprising hexagonal boron nitride and cubic boron nitride.
    Type: Application
    Filed: July 20, 2011
    Publication date: May 23, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kotaro Miyatani, Takenao Nemoto, Takuya Kurotori, Yasuo Kobayashi, Toshihisa Nozawa
  • Patent number: 8398813
    Abstract: The present invention provides a processing apparatus and a processing method, both of which can carry out a low-temperature process to allow active gas species to react with an oxide film on an object to be processed to form a product film and a heating process to heat the object to a predetermined temperature to evaporate the product film, in succession. This processing apparatus 12 is provided with a shielding plate 103 capable of entering a gap between the object W and a transparent window 28 and also withdrawing from the gap. On condition that the shielding plate 103 is closed to cut off irradiation heat from the transparent window 28, the product film is formed by allowing the active gas species of NF3 gas to react with a native oxide film on the object under the low-temperature condition. After that, upon closing the shielding plate 103, the native oxide film is removed by applying heat irradiated from a heating lamp 36 to the product film through the transparent window 28.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: March 19, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Yasuo Kobayashi, Masao Yoshioka
  • Patent number: 8349370
    Abstract: The present invention provides a bloat controlling agent for a ruminant, comprising cashew nut shell liquid.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: January 8, 2013
    Assignee: National University Corporation Hokkaido University
    Inventors: Yasuo Kobayashi, Kyo Nagashima, Masami Mochizuki
  • Patent number: 8264897
    Abstract: A static random access memory includes: a memory cell connected with a pair of bit lines and supplied with a power supply voltage from a first power supply; a precharge circuit configured to precharge the pair of bit lines with a precharge voltage; and a voltage reducing circuit including: a control circuit comprising a differential amplifier circuit configured to amplify a difference input of a reference voltage generated through resistance division of the power supply voltage and the precharge voltage supplied to a node to output a control signal; and a voltage reduction control transistor connected between the node and the first power supply and configured to generate the precharge voltage in response to the control signal. The precharge circuit includes: precharge transistors configured to control supply of the precharge voltage to the bit lines in response to a first precharge control signal.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: September 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yasuo Kobayashi
  • Publication number: 20110318919
    Abstract: A method for manufacturing semiconductor devices includes the steps of annealing an insulating layer and forming a barrier layer including a metal element over the insulating layer. The insulating layer includes a fluorocarbon (CFx) film. The barrier layer is formed by a high-temperature sputtering process after the annealing step.
    Type: Application
    Filed: January 22, 2010
    Publication date: December 29, 2011
    Applicant: Tokyo Electron Limited
    Inventors: Masahiro Horigome, Takuya Kurotori, Yasuo Kobayashi, Takaaki Matsuoka, Toshihisa Nozawa
  • Publication number: 20110252416
    Abstract: A device driver setting device includes an acquiring unit, an allowing unit, and a writing unit. The acquiring unit acquires, from a data group constituting a device driver, condition information for each of one or more items which the device driver refers to. The condition information for each of the one or more items indicates a condition which can be taken by a setting value to be set in each of the items. The allowing unit allows a user to select a setting value which is to be set in each of at least a part of the items acquired, in accordance with the condition information associated with each of the at least a part of the items acquired. The writing unit writes setting values which are to be set in the respective items acquired into the data group based on a result of the selecting.
    Type: Application
    Filed: November 11, 2010
    Publication date: October 13, 2011
    Applicant: FUJI XEROX CO., LTD.
    Inventor: Yasuo KOBAYASHI
  • Publication number: 20110235387
    Abstract: A semiconductor memory device provided with a new bit line hierarchization method that enables further reduction of power consumption is provided. The semiconductor memory device includes multiple memory blocks provided in a matrix configuration and multiple main bit lines provided in correspondence with the memory blocks. Each of the memory blocks includes: multiple memory cells provided in a matrix configuration; multiple sub bit lines provided on a column-by-column basis; multiple word lines provided with respect to each of columns and rows and common to multiple memory blocks; and a switch circuit that couples a corresponding main bit line to any of the sub bit lines. In the operation of reading a target cell as the target of read, a main bit line corresponding to the target cell is selected, a sub bit line corresponding to the column of the target cell is selected through the switch circuit; and a word line corresponding to the column and the row of the target cell is selected from among the word lines.
    Type: Application
    Filed: February 25, 2011
    Publication date: September 29, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuo KOBAYASHI
  • Patent number: 8017197
    Abstract: A microwave is radiated into a processing chamber (1) from a planar antenna member of an antenna (7) through a dielectric plate (6). With this, a C5F8 gas supplied into the processing chamber (1) from a gas supply member (3) is changed (activated) into a plasma so as to form a fluorine-containing carbon film of a certain thickness on a semiconductor wafer (W). Each time a film forming process of forming a film on one wafer is carried out, a cleaning process and a pre-coating process are carried out. In the cleaning process, the inside of the processing chamber is cleaned with a plasma of an oxygen gas and a hydrogen gas. In the pre-coating process, the C5F8 gas is changed into a plasma, and a pre-coat film of fluorine-containing carbon thinner than the fluorine-containing carbon film formed in the film forming process is formed.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: September 13, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Yasuo Kobayashi, Kohei Kawamura
  • Patent number: 7897205
    Abstract: A film forming method is characterized in that the method is provided with a step of introducing a processing gas including inorganic silane gas into a processing chamber, in which a mounting table composed of ceramics including a metal oxide is arranged, and precoating an inner wall of the processing chamber including a surface of the mounting table with a silicon-containing nonmetal thin film; a step of mounting a substrate to be processed on the mounting table precoated with the nonmetal thin film; and a step of introducing a processing gas including organic silane gas into the processing chamber, and forming a silicon-containing nonmetal thin film on a surface of the substrate mounted on the mounting table.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: March 1, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Takatoshi Kameshima, Kohei Kawamura, Yasuo Kobayashi
  • Publication number: 20100296354
    Abstract: A static random access memory includes: a memory cell connected with a pair of bit lines and supplied with a power supply voltage from a first power supply; a precharge circuit connected with the pair of bit lines and configured to precharge the pair of bit lines with a precharge voltage; and a voltage reducing circuit connected between the precharge circuit and the first power supply. The voltage reducing circuit includes: a control circuit comprising a differential amplifier circuit which is configured to amplify a difference input of a reference voltage generated through resistance division of the power supply voltage and the precharge voltage supplied to a node to output a control signal; and a voltage reduction control transistor connected between the node and the first power supply and configured to generate the precharge voltage in response to the control signal.
    Type: Application
    Filed: May 18, 2010
    Publication date: November 25, 2010
    Inventor: Yasuo KOBAYASHI
  • Publication number: 20100264115
    Abstract: Provided is a holding stage structure which holds a substrate and disposed in a process chamber that is vacuum-evacuatable and allows a predetermined process to be performed on the substrate therein. The holding stage structure includes: a holding stage body on which the substrate is placed; an elevation pin mechanism lowering the substrate on the holding stage body or raising the substrate from the holding stage body; and a stepped portion formed on the holding stage body so that a peripheral portion of a rear surface of the substrate placed on the holding stage body is exposed to a processing gas supplied into the process chamber.
    Type: Application
    Filed: February 4, 2008
    Publication date: October 21, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kohei Kawamura, Yasuo Kobayashi, Toshihisa Nozawa, Kiyotaka Ishibashi
  • Publication number: 20100249058
    Abstract: To provide safe and easy means for preventing or treating diseases of birds and mammals, in particular, livestock. In particular, to provide means for preventing or treating an infectious disease caused by a Gram-positive bacterium. In addition, to improve fermentation in the rumen of a ruminant animal, to contribute to suppression of the generation of greenhouse gas, and to increase the feed efficiency. Mannosylerythritol lipids (MEL) and/or rhamnolipids are given to birds or mammals.
    Type: Application
    Filed: October 11, 2007
    Publication date: September 30, 2010
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Shinji Ito, Motoshi Suzuki, Kuniko Suzuki, Yasuo Kobayashi
  • Patent number: 7803705
    Abstract: A dielectric film (91) made of CF is deposited on a substrate. A protective layer comprising an SiCN film (93) is formed on the dielectric film (91). A film (94) serving as a hardmask made of SiCO is deposited on the protective layer by a plasma containing active species of silicon, carbon, and oxygen. When the protective layer is formed, an SiC film (92) is deposited on the dielectric film (91) by a plasma containing active species of silicon and carbon, and thereafter the SiCN film (93) is deposited on the SiC film (92) by a plasma containing active species of silicon, carbon, and nitrogen.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: September 28, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Yasuo Kobayashi, Kenichi Nishizawa, Takatoshi Kameshima, Takaaki Matsuoka
  • Patent number: 7776736
    Abstract: Disclosed are a substrate for electronic devices such as semiconductor devices and a method for processing the same, In the processing method, firstly a substrate for electronic devices is prepared and an insulating film (I) composed of a fluorocarbon (CF) is formed on the surface of the substrate. Then, fluorine (F) atoms exposed in the surface of the insulating film (I) are removed therefrom by bombarding the surface of the insulating film (I) with, for example, active species (KR+) produced in a krypton (Kr) gas plasma. In this connection, the substrate is kept out of contact with moisture at least from immediately after the insulating film forming step until completion of the fluorine removing step.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: August 17, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Yasuo Kobayashi, Kohei Kawamura
  • Publication number: 20100183756
    Abstract: The present invention provides a rumen fermentation improving agent, comprising cashew nut shell liquid.
    Type: Application
    Filed: June 6, 2008
    Publication date: July 22, 2010
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Yasuo Kobayashi, Kyo Nagashima, Masami Mochizuki