Patents by Inventor Yasuo Yamaguchi

Yasuo Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060089232
    Abstract: A drive apparatus for a hybrid vehicle is provided with a motor, a clutch that transmits and cuts off a driving force between the motor and an engine, and a control device that performs an operation control for the motor and the clutch. If there is an engine start request during driving of a wheel by the motor, the control device increases an operating pressure of the clutch to start the transmission of torque from the motor to the engine side, and detects a transmission torque to be transmitted via the clutch. The control device also performs a control that sets an output torque of the motor as equal to a torque that is the sum of the transmission torque and a request torque for wheel driving, which is determined based upon an accelerator opening.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 27, 2006
    Applicant: Aisin AW Co., Ltd.
    Inventors: Yasuhiko Kobayashi, Yasuo Yamaguchi
  • Publication number: 20060086934
    Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.
    Type: Application
    Filed: December 5, 2005
    Publication date: April 27, 2006
    Applicant: RENESAS TECHNOLOGY, INC.
    Inventors: Toshiaki Iwamatsu, Yasuo Yamaguchi, Shigenobu Maeda, Shoichi Miyamoto, Akihiko Furukawa, Yasuo Inoue
  • Publication number: 20060055084
    Abstract: The present invention is to provide a process for producing a composite of an aluminum material and a synthetic resin molding that can be produced at a high efficiency and to provide a stable and fast composite that is large in a peel strength and a mechanical strength. The process for producing a composite according to the present invention is characterized in that an aluminum raw material is oxidized in an electrolytic bath of phosphoric acid or sodium hydride, thereby an anodic oxidation coating provided with innumerable pores 3 having a diameter of 25 nm or more made open in the surface thereof is formed thereon, and a synthetic resin mold 6 is coupled with the anodic oxidation coating 2 in such a condition that the part 6a thereof is intruded in the innumerable pores.
    Type: Application
    Filed: December 12, 2003
    Publication date: March 16, 2006
    Applicant: Corona International Corporation
    Inventors: Takashi Yamaguchi, Minobu Yamaguchi, Akiko Uematsu, Masao Yamaguchi, Yasuo Yamaguchi
  • Patent number: 7012389
    Abstract: An electric drive control apparatus for an electric machine, includes a controller that computes an instruction value based on an electric machine rotational speed and a target electric machine torque that represents a target value of an electric machine torque, generates a drive signal based on the instruction value, computes a voltage saturation variable that represents a likelihood of an occurrence of a voltage saturation, determines whether a switch condition for switching a control between an asynchronous PWM control and a synchronous PWM control is met based on the voltage saturation variable, and selects and outputs the drive signal and switches the control between the asynchronous PWM control and the synchronous PWM control based on a determination as to the switch condition.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: March 14, 2006
    Assignee: Aisin AW Co., Ltd.
    Inventors: Yasuhiko Kobayashi, Yasuo Yamaguchi
  • Patent number: 7009277
    Abstract: To improve the radiation property without inhibiting miniaturization of the device, heat generated at a heat generating layer (5) is radiated to a substrate (1) via plugs (7, 17), wiring layers (8, 18), and plugs (9, 19). A cross sectional along the principal plane of the substrate (1) of the plugs (7, 9, 17, 19) is set to be a rectangle, and the long sides of the rectangle are parallel to the direction perpendicular to the direction connecting one end and the other end of the heat generating layer (5). Between the plugs (9, 19) and the semiconductor layer (2) is interposed n-type semiconductor layers (3, 13).
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: March 7, 2006
    Assignee: Renesas Technology Corp.
    Inventor: Yasuo Yamaguchi
  • Patent number: 7006906
    Abstract: An electric drive control apparatus which prevents the voltage from being saturated and does not cause the driver to feel uncomfortable during driving.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: February 28, 2006
    Assignee: Aisin Aw Co., Ltd.
    Inventors: Yasuhiko Kobayashi, Yasuo Yamaguchi
  • Patent number: 7001822
    Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: February 21, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Yasuo Yamaguchi, Shigenobu Maeda, Shoichi Miyamoto, Akihiko Furukawa, Yasuo Inoue
  • Patent number: 6988407
    Abstract: An acceleration sensor includes an acceleration sensor element and a frame portion surrounding the element. The sensor element and the frame portion are located on a major surface of a substrate. An intermediate layer is formed on the frame portion. A cap portion is bonded to the intermediate layer, thereby sealing-off the acceleration sensor element. Grooves in the form of a frame are provided in the frame portion and the intermediate layer, respectively, and located at positions generally identical to each other with regard to the major surface direction of the substrate.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: January 24, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Kunihiro Nakamura
  • Publication number: 20060005625
    Abstract: An acceleration sensor includes a semiconductor substrate, a sensing element formed on the semiconductor substrate, a bonding frame made of polysilicon which is formed on the semiconductor substrate and surrounds the sensing element, and a glass cap which is bonded to a top surface of the bonding frame made of polysilicon to cover the sensing element above the sensing element while being spaced by a predetermined distance from the sensing element. The bonding frame made of polysilicon is not doped with any impurity.
    Type: Application
    Filed: September 7, 2005
    Publication date: January 12, 2006
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Yasuo Yamaguchi
  • Patent number: 6958266
    Abstract: A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: October 25, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Takuji Matsumoto, Shoichi Miyamoto
  • Patent number: 6953979
    Abstract: A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: October 11, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Takuji Matsumoto, Shoichi Miyamoto
  • Patent number: 6953993
    Abstract: An acceleration sensor includes a semiconductor substrate, a sensing element formed on the semiconductor substrate, a bonding frame made of polysilicon which is formed on the semiconductor substrate and surrounds the sensing element, and a glass cap which is bonded to a top surface of the bonding frame made of polysilicon to cover the sensing element above the sensing element while being spaced by a predetermined distance from the sensing element. The bonding frame made of polysilicon is not doped with any impurity.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: October 11, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yasuo Yamaguchi
  • Publication number: 20050212056
    Abstract: To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST21), a polysilicon film (PS21) is selectively provided on the trench isolation oxide film (ST21), a silicon layer (S22) is provided on the polysilicon film (PS21), and a side wall spacer (SW2) is provided on a side surface of the polysilicon film (PS21). The polysilicon film (PS21) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR11) and an N-type well region (WR12) in an SOI layer 3 across the two well regions.
    Type: Application
    Filed: May 24, 2005
    Publication date: September 29, 2005
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Hideki Naruoka, Nobuyoshi Hattori, Shigeto Maegawa, Yasuo Yamaguchi, Takuji Matsumoto
  • Publication number: 20050184342
    Abstract: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.
    Type: Application
    Filed: April 19, 2005
    Publication date: August 25, 2005
    Applicant: Renesas Technology Corp.
    Inventors: Yuuichi Hirano, Shigeto Maegawa, Toshiaki Iwamatsu, Takuji Matsumoto, Shigenobu Maeda, Yasuo Yamaguchi
  • Publication number: 20050156242
    Abstract: A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.
    Type: Application
    Filed: January 14, 2005
    Publication date: July 21, 2005
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yasuo Yamaguchi, Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Takuji Matsumoto, Shoichi Miyamoto
  • Patent number: 6914307
    Abstract: A semiconductor device includes a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, semiconductor elements being electrically isolated from each other by the isolation film. The semiconductor device also includes a PN junction portion provided under the isolation film and formed by two semiconductor regions of different conductivity types in the semiconductor layer. The isolation film includes a nitride film provided in a position corresponding to a top of the PN junction portion and has a substantially uniform thickness across the two semiconductor regions and an upper oxide film and a lower oxide film which are provided in upper and lower portions of the nitride film. The surface of the semiconductor layer is silicidized in such a state that a surface of the isolation film is exposed.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: July 5, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Hideki Naruoka, Nobuyoshi Hattori, Shigeto Maegawa, Yasuo Yamaguchi, Takuji Matsumoto
  • Publication number: 20050126290
    Abstract: An acceleration sensor includes a semiconductor substrate, a sensing element formed on the semiconductor substrate, a bonding frame made of polysilicon which is formed on the semiconductor substrate and surrounds the sensing element, and a glass cap which is bonded to a top surface of the bonding frame made of polysilicon to cover the sensing element above the sensing element while being spaced by a predetermined distance from the sensing element. The bonding frame made of polysilicon is not doped with any impurity.
    Type: Application
    Filed: June 3, 2004
    Publication date: June 16, 2005
    Inventor: Yasuo Yamaguchi
  • Patent number: 6906442
    Abstract: A motor has a rotatably supported rotor core and permanent magnets disposed at equal intervals at a plurality of positions in a circumferential direction of the rotor core. The rotor core has projecting poles formed at equal intervals at a center between each permanent magnet. Furthermore, an opening angle center line of each projecting pole conforms to a center line of an angle created by each opening angle center line of two adjacent permanent magnets. Additionally, each projecting pole is shaped asymmetrical to a line connecting a center of the projecting pole in the rotational direction of the rotor core and an axis center of the rotor core.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: June 14, 2005
    Assignee: Aisin AW Co., Ltd.
    Inventor: Yasuo Yamaguchi
  • Patent number: 6888243
    Abstract: To improve the radiation property without inhibiting miniaturization of the device, heat generated at a heat generating layer (5) is radiated to a substrate (1) via plugs (7, 17), wiring layers (8, 18), and plugs (9, 19). A cross sectional along the principal plane of the substrate (1) of the plugs (7, 9, 17, 19) is set to be a rectangle, and the long sides of the rectangle are parallel to the direction perpendicular to the direction connecting one end and the other end of the heat generating layer (5). Between the plugs (9, 19) and the semiconductor layer (2) is interposed n-type semiconductor layers (3, 13).
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: May 3, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Yasuo Yamaguchi
  • Patent number: 6882006
    Abstract: A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: April 19, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Shigenobu Maeda, Yasuo Yamaguchi, Hirotada Kuriyama, Shigeto Maegawa