Patents by Inventor Yasushi Goto
Yasushi Goto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040259361Abstract: A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.Type: ApplicationFiled: January 12, 2004Publication date: December 23, 2004Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Patent number: 6833296Abstract: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.Type: GrantFiled: February 12, 2004Date of Patent: December 21, 2004Assignee: Renesas Technology Corp.Inventors: Jiro Yugami, Natsuki Yokoyama, Toshiyuki Mine, Yasushi Goto
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Publication number: 20040238100Abstract: A piezoelectric ceramic composition including three components, Pb(Zn1/3Nb2/3)O3, PbTiO3, and PbZrO3, and having a basic composition formula of Pb(Zn1/3Nb2/3)xZryTizO3, where 0.90<x+y+z<1.0, exhibits excellent piezoelectric characteristics and heat resistance and has a low sintering temperature of about 900° C., a coupling coefficient Kp not less than 0.50, and a Curie temperature not lower than 300° C. A piezoelectric device using this composition may employ inexpensive silver and silver-palladium alloys containing a high percentage of silver as material of an internal electrode, thus being inexpensive and having excellent characteristics.Type: ApplicationFiled: March 15, 2004Publication date: December 2, 2004Inventors: Seiichi Minami, Yasushi Goto, Kazuhiro Okuda
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Publication number: 20040198019Abstract: In order to achieve an isolation trench formation process according to the present invention in which the structure of a silicon nitride film liner can be easily controlled and to allow both of reduction of the device feature length and reduction in stress occurring in an isolation trench, the silicon nitride film liner is first deposited on the inner wall of the trench formed on a silicon substrate. The upper surface of a first embedded insulator film for filling the inside of the trench is recessed downward so as to expose an upper end portion of the silicon nitride film liner. Next, the exposed portion of the silicon nitride film liner is converted into non-silicon-nitride type insulator film, such as a silicon oxide film. A second embedded insulator film is then deposited on the upper portion of the first embedded insulator film, and the deposited surface is then planarized.Type: ApplicationFiled: April 1, 2004Publication date: October 7, 2004Applicant: Renesas Technology Corp.Inventors: Kan Yasui, Toshiyuki Mine, Yasushi Goto, Natsuki Yokoyama
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Patent number: 6797566Abstract: A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed in first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.Type: GrantFiled: January 16, 2002Date of Patent: September 28, 2004Assignees: Renesas Technology Corp., Hitachi Device Engineering Corp. Ltd.Inventors: Takashi Kobayashi, Yasushi Goto, Tokuo Kure, Hideaki Kurata, Hitoshi Kume, Katsutaka Kimura, Syunichi Saeki
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Publication number: 20040159889Abstract: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.Type: ApplicationFiled: February 12, 2004Publication date: August 19, 2004Inventors: Jiro Yugami, Natsuki Yokoyama, Toshiyuki Mine, Yasushi Goto
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Patent number: 6717766Abstract: Provides an automatic changer with excellent space efficiency, by reducing the size of a hand mechanism section that is mounted with a CCD. The automatic changer selects and holds one desired cartridge from among one of accommodation cells provided in a magazine, conveys this selected cartridge to a recording/reproducing apparatus, and reads a bar code label adhered to the side surface of the cartridge thereby to identify the cartridge. The automatic changer has the CCD that reads a bar code disposed in the inner part of a casing that movably accommodates a hand mechanism section for holding the cartridge. The automatic changer also has a condenser lens for focusing the image of the bar code on the CCD disposed at one part of the hand mechanism section. With this arrangement, the automatic changer moves the hand mechanism section to the front of the cartridge accommodated in the accommodation cell, and focuses the image of the bar code on the CCD. Then, the CCD identifies the contents of the cartridge.Type: GrantFiled: May 10, 2002Date of Patent: April 6, 2004Assignee: Fujistu LimitedInventors: Koujirou Hashimoto, Kenichi Utsumi, Yuji Kato, Kazuhiko Kawase, Satoshi Kanbayashi, Yasushi Goto
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Patent number: 6714293Abstract: An exposure meter has both function of an incident light type exposure meter for measuring an exposure value of an object by an incident light to the object and a reflected light type exposure meter for measuring exposure value of the object by a reflected light from the object. A latitude of a film is calculated from the exposure value by the incident light. The exposure value by the incident light and an upper and a lower limit values of the latitude are displayed on a display device. At least one exposure value measured by the reflected light is further displayed on the display device comparably with the latitude.Type: GrantFiled: September 7, 2001Date of Patent: March 30, 2004Assignee: Minolta Co., Ltd.Inventors: Yasushi Goto, Yoshio Yuasa
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Publication number: 20040058541Abstract: To meet the requirements for ever smaller semiconductor devices, it is required to provide a sample surface processing method which is capable of processing a device of 1 micron or less, or more preferably 0.5 micron or less. It is also required to provide a surface processing method which allows a flat surface to be etched without irregularities occurring on the etched surface, and permits the multilayer film to be etched without underlying oxide film etched through.Type: ApplicationFiled: September 29, 2003Publication date: March 25, 2004Inventors: Tetsuo Ono, Takafuml Tokunaga, Tadashi Umezawa, Motohiko Yoshigai, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takashi Sato, Yasushi Goto
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Patent number: 6710383Abstract: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.Type: GrantFiled: December 7, 2001Date of Patent: March 23, 2004Assignee: Renesas Technology CorporationInventors: Jiro Yugami, Natsuki Yokoyama, Toshiyuki Mine, Yasushi Goto
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Patent number: 6677244Abstract: A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.Type: GrantFiled: May 1, 2002Date of Patent: January 13, 2004Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Patent number: 6660647Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.Type: GrantFiled: January 11, 2001Date of Patent: December 9, 2003Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Takafumi Tokunaga, Tadashi Umezawa, Motohiko Yoshigai, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takashi Sato, Yasushi Goto
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Publication number: 20030030938Abstract: Provides an automatic changer with excellent space efficiency, by reducing the size of a hand mechanism section that is mounted with a CCD. The automatic changer selects and holds one desired cartridge from among one of accommodation cells provided in a magazine, conveys this selected cartridge to a recording/reproducing apparatus, and reads a bar code label adhered to the side surface of the cartridge thereby to identify the cartridge. The automatic changer has the CCD that reads a bar code disposed in the inner part of a casing that movably accommodates a hand mechanism section for holding the cartridge. The automatic changer also has a condenser lens for focusing the image of the bar code on the CCD disposed at one part of the hand mechanism section. With this arrangement, the automatic changer moves the hand mechanism section to the front of the cartridge accommodated in the accommodation cell, and focuses the image of the bar code on the CCD. Then, the CCD identifies the contents of the cartridge.Type: ApplicationFiled: May 10, 2002Publication date: February 13, 2003Applicant: Fujitsu LimitedInventors: Koujirou Hashimoto, Kenichi Utsumi, Yuji Kato, Kazuhiko Kawase, Satoshi Kanbayashi, Yasushi Goto
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Patent number: 6492277Abstract: Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.Type: GrantFiled: September 10, 1999Date of Patent: December 10, 2002Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Patent number: 6456681Abstract: A neutron flux measuring apparatus, adapted to a boiling-water reactor (BWR) of a nuclear power plant and an advanced boiling-water reactor (ABWR) of a nuclear power plant, for measuring a neutron flux in a reactor pressure vessel, comprises a neutron flux detector assembly incorporating a local power range monitor detector assembly and a start-up range neutron monitor detector, a preamplifier amplifying a detector signal obtained from said start-up range neutron monitor detector, a start-up range neutron monitor operation unit operating, indicating and monitoring the amplified signal of the start-up range neutron monitor detector, and a local power range monitor operation unit operating, indicating and monitoring a signal obtained from the local power range monitor detector.Type: GrantFiled: August 31, 1999Date of Patent: September 24, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Yasushi Goto, Nobuaki Oono, Yuki Narawa, Teruji Tarumi, Koji Hirukawa
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Patent number: 6448698Abstract: A laminated piezoelectric transformer according to the present invention comprises (a) a laminated body formed by laminating a plurality of ceramic layers and a plurality of internal electrodes and (b) a plurality of external electrodes electrically connected with the internal electrodes and disposed on the surface of the laminated body. Further, the internal electrodes of the laminated piezoelectric transformer of the invention are characterized by having a plurality of primary internal electrodes positioned at the middle portion along the longitudinal direction of the laminated body and a plurality of secondary internal electrodes positioned at both end portions of the laminated body. By virtue of this configuration of the invention, the polarization volume on the secondary side can be enlarged and, therefore, the laminated piezoelectric transformer of the invention can step up voltages at high energy conversion efficiency.Type: GrantFiled: February 21, 2001Date of Patent: September 10, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazuhiro Okuda, Yasushi Goto, Seiichi Minami, Tomokazu Yamaguchi, Satoshi Kawamura, Kunitoshi Kawano, Hiroshi Fukushima
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Publication number: 20020123229Abstract: A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.Type: ApplicationFiled: May 1, 2002Publication date: September 5, 2002Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Publication number: 20020122522Abstract: A neutron flux measuring apparatus, adapted to a boiling-water reactor (BWR) of a nuclear power plant and an advanced boiling-water reactor (ABWR) of a nuclear power plant, for measuring a neutron flux in a reactor pressure vessel, comprises a neutron flux detector assembly incorporating a local power range monitor detector assembly and a start-up range neutron monitor detector, a preamplifier amplifying a detector signal obtained from said start-up range neutron monitor detector, a start-up range neutron monitor operation unit operating, indicating and monitoring the amplified signal of the start-up range neutron monitor detector, and a local power range monitor operation unit operating, indicating and monitoring a signal obtained from the local power range monitor detector.Type: ApplicationFiled: August 31, 1999Publication date: September 5, 2002Inventors: YASUSHI GOTO, NOBUAKI OONO, YUKI NARAWA, TERUJI TARUMI, KOJI HIRUKAWA
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Publication number: 20020072180Abstract: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.Type: ApplicationFiled: December 7, 2001Publication date: June 13, 2002Inventors: Jiro Yugami, Natsuki Yokoyama, Toshiyuki Mine, Yasushi Goto
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Publication number: 20020030806Abstract: An exposure meter has both function of an incident light type exposure meter for measuring an exposure value of an object by an incident light to the object and a reflected light type exposure meter for measuring exposure value of the object by a reflected light from the object. A latitude of a film is calculated from the exposure value by the incident light. The exposure value by the incident light and an upper and a lower limit values of the latitude are displayed on a display device. At least one exposure value measured by the reflected light is further displayed on the display device comparably with the latitude.Type: ApplicationFiled: September 7, 2001Publication date: March 14, 2002Inventors: Yasushi Goto, Yoshio Yuasa