Patents by Inventor Yasushi Sasaki
Yasushi Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10180597Abstract: The invention provides a liquid crystal display device, as well as a polarizer and a protective film suitable for the liquid crystal display device. The liquid crystal display device comprises a backlight light source, two polarizers, and a liquid crystal cell disposed between the two polarizers; the backlight light source being a white light-emitting diode light source; each of the two polarizers comprising a polarizing film and protective films laminated on both sides of the polarizing film; at least one of the protective films being a polyester film having an adhesion-facilitating layer; the polyester film having a retardation of 3,000 to 30,000 nm; and the adhesion-facilitating layer comprising a polyester resin (A) and a polyvinyl alcohol resin (B).Type: GrantFiled: May 16, 2012Date of Patent: January 15, 2019Assignee: TOYOBO CO., LTD.Inventors: Kouichi Murata, Mitsuharu Nakatani, Yasushi Sasaki
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Publication number: 20180346732Abstract: The present invention relates to a turmeric pigment composition. More specifically, the present invention provides a turmeric pigment composition in which aggregation and sedimentation of a turmeric pigment over time is effectively prevented even when a concentrated amount of turmeric pigment is incorporated in a solvent; the turmeric pigment composition also ensures a desirable color-developing property, and is capable of stably adding a deep color with a bright tone, which was never accomplished by a hitherto-known colorant.Type: ApplicationFiled: June 15, 2018Publication date: December 6, 2018Applicant: SAN-EI GEN F.F.I., INC.Inventors: Takeshi Miuchi, Masayuki Nishino, Yasushi Sasaki, Takashi Morimoto, Yoshiharu Tanaka
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Patent number: 10023745Abstract: [Object] The present invention relates to a turmeric pigment composition. More specifically, the present invention provides a turmeric pigment composition in which aggregation and sedimentation of a turmeric pigment over time is effectively prevented even when a concentrated amount of turmeric pigment is incorporated in a solvent; the turmeric pigment composition also ensures a desirable color-developing property, and is capable of stably adding a deep color with a bright tone, which was never accomplished by a hitherto-known colorant.Type: GrantFiled: September 28, 2009Date of Patent: July 17, 2018Assignee: SAN-EI GEN F.F.I., INC.Inventors: Takeshi Miuchi, Masayuki Nishino, Yasushi Sasaki, Takashi Morimoto, Yoshiharu Tanaka
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Patent number: 10006151Abstract: Provided is a fragrance-retaining fiber that, after absorption of a fragrance component, retains the fragrance even though a long period of time has passed. In particular, provided is a fragrance-retaining polyurethane-based fiber having, 48 hours after absorption of a fragrance component, a total fragrance component emission of from 0.1 ?g/g·h to 1000 ?g/g·h.Type: GrantFiled: January 17, 2014Date of Patent: June 26, 2018Assignee: TORAY OPELONTEX CO., LTD.Inventors: Toshihiro Tanaka, Yasushi Sasaki, Koji Hirano, Yasushi Fujita, Fumitake Mori
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Publication number: 20180173038Abstract: Provided is a liquid crystal display device that has excellent visibility while using a protective film comprising a polyester film. The liquid crystal display device comprises a backlight light source, and a liquid crystal cell disposed between two polarizers; the backlight light source being a white light-emitting diode; each of the polarizers comprising a polarizing film and protective films laminated on both sides of the polarizing film; and at least one of the protective films being a polyester film having a retardation of 3,000 to 30,000 nm.Type: ApplicationFiled: January 3, 2018Publication date: June 21, 2018Applicant: Toyobo Co., Ltd.Inventors: Koichi MURATA, Yasushi SASAKI
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Publication number: 20180149911Abstract: A drive circuit of a display device includes a TFT having a source electrode 15, a drain electrode 14, and a gate electrode 13. Provided is an electrically isolated light-shielding film 12 which has a main body portion for shielding a channel portion of the TFT, and an extension portion 20 formed integrally with the main body portion. An auxiliary capacitor C2 is formed by overlapping, in a planar view, the extension portion 20 with an electrode member 21 formed integrally with the source electrode 15. In place of the electrode member 21, an electrode member formed in a same layer as the channel portion and connected to the source electrode 15, an electrode member connected to one conduction electrode of another TFT, or an electrode member formed integrally with the gate electrode 13 may be used. With this, a small-area and low-cost drive circuit including a light-shielded thin film transistor is provided.Type: ApplicationFiled: May 18, 2016Publication date: May 31, 2018Applicant: SHARP KABUSHIKI KAISHAInventors: TAKAHIRO YAMAGUCHI, SHIGE FURUTA, JUNICHI YAMADA, HIDEKAZU YAMANAKA, YUHICHIROH MURAKAMI, YASUSHI SASAKI
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Publication number: 20180144702Abstract: Provided is a shift register circuit capable of preventing occurrence of malfunction caused by a threshold shift of a thin-film transistor due to an influence of external light. A unit circuit constituting each stage of the shift register circuit includes a plurality of thin-film transistors. The plurality of thin-film transistors are categorized into a first group (T2, T4, T9) whose on-off state is controlled at relatively high on-duty and a second group (T1, T3, T5, T6, T7, T8) whose on-off state is controlled at relatively low on-duty. In such a configuration, a light shielding film (LS) is provided only for the thin-film transistor included in one of the first group and the second group.Type: ApplicationFiled: May 18, 2016Publication date: May 24, 2018Inventors: SHIGE FURUTA, TAKAHIRO YAMAGUCHI, JUNICHI YAMADA, HIDEKAZU YAMANAKA, YASUSHI SASAKI, YUHICHIROH MURAKAMI
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Publication number: 20180137831Abstract: A unit circuit 11 of a shift register is provided with a transistor Tr10 for supplying an off potential to a node n1 via a drain terminal when performing an all-on output. An all-on control signal AON is supplied to a gate terminal of the transistor Tr10. Instead of a low level potential VSS supplied from a power supply circuit, an initialization signal INIT which becomes a low level when performing the all-on output supplied to a source terminal of the transistor Tr10. Since the all-on signal AON and the initialization signal INIT are supplied from an outside, even if noise is imposed on the low level potential VSS when performing the normal operation, the transistor Tr10 does not turn on and charge does not escape from the node 1. With this, it is possible to prevent malfunction of the shift register due to noise imposed on the off potential supplied from the power supply circuit.Type: ApplicationFiled: April 21, 2016Publication date: May 17, 2018Inventors: YUHICHIROH MURAKAMI, SHIGE FURUTA, HIDEKAZU YAMANAKA, YASUSHI SASAKI
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Publication number: 20180122320Abstract: A unit circuit 11 of a shift register is provided with a transistor Tr8 having a drain terminal connected to a node N2, a source terminal to which an off potential is applied, and a gate terminal connected to an output terminal OUT, in order to stabilize a potential of the node N2. The unit circuit 11 is further provided with a transistor Tr9 having a drain terminal connected to the output terminal OUT, a source terminal to which the off potential is applied, and a gate terminal to which an initialization signal INIT is supplied. With this, when performing an initialization, it is possible to control the potential of the node N2 to be a desired level and initialize the shift register certainly, irrespective of a state of the transistor Tr8 before the initialization.Type: ApplicationFiled: April 21, 2016Publication date: May 3, 2018Inventors: YASUSHI SASAKI, YUHICHIROH MURAKAMI, SHIGE FURUTA, HIDEKAZU YAMANAKA
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Patent number: 9897857Abstract: Provided is a liquid crystal display device that has excellent visibility while using a protective film comprising a polyester film. The liquid crystal display device comprises a backlight light source, and a liquid crystal cell disposed between two polarizers; the backlight light source being a white light-emitting diode; each of the polarizers comprising a polarizing film and protective films laminated on both sides of the polarizing film; and at least one of the protective films being a polyester film having a retardation of 3,000 to 30,000 nm.Type: GrantFiled: March 31, 2017Date of Patent: February 20, 2018Assignee: Toyobo Co., Ltd.Inventors: Koichi Murata, Yasushi Sasaki
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Patent number: 9881688Abstract: A shift register is realized having a simple construction with which it is possible to switch the scanning order of gate bus lines and the occurrence of an erroneous operation caused by a threshold voltage drop can be prevented. Unit circuits that make up the shift register are configured of: a thin film transistor in which a third clock is supplied to the gate terminal, the drain terminal is connected to a first node, and a first input signal (output signal of prior stage) is supplied to the source terminal; a thin film transistor in which a second clock is supplied to the gate terminal, the drain terminal is connected to the first node, and a second input signal (output signal of subsequent stage) is supplied to the source terminal; and a thin film transistor in which the gate terminal is connected to the first node, a first clock is supplied to the drain terminal, and the source terminal is connected to an output terminal.Type: GrantFiled: September 27, 2013Date of Patent: January 30, 2018Assignee: SHARP KABUSHIKI KAISHAInventors: Yasushi Sasaki, Yuhichiroh Murakami, Shuji Nishi
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Publication number: 20180012540Abstract: The present invention reliably and sufficiently corrects a voltage variation in data signal lines in a display device resulting when sampling analog video signals, while suppressing increase in layout area. In a data signal line drive circuit of an active matrix liquid crystal display device, a video signal Svi is sampled by an Nch transistor (SWk) which has a parasitic capacitance (Cgd) that causes a voltage drop in a data signal line SL3(i?1)+k (i=1 through n; k=1, 2, 3). To correct this, an inversion delayer (342) makes logical inversion of the transistor (SWk)'s control signal Sck and delays the inverted signal for a predetermined time to generate an inversion delayed signal Srdk, and applies this inversion delayed signal Srd to the data signal line 3(i?1)+k via a correction capacitance element (Cc). The inversion delayer (342) makes the inversion delayed signal Srdk start its change from an L level voltage to a H level voltage after the Nch transistor (SWk) has assumed an OFF state.Type: ApplicationFiled: January 27, 2016Publication date: January 11, 2018Inventors: KOHEI HOSOYACHI, YUHICHIROH MURAKAMI, YASUSHI SASAKI
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Patent number: 9842559Abstract: A demultiplexer circuit (12) of a display device according to one aspect of the present invention includes signal input lines (Vn), control lines (BSW, GSW, and RSW), and sampling transistors (13R2, 13G2, and 13B1). Sampling transistors connected to one signal input line includes first and second sampling transistors. A first sampling transistor (13B1) includes a control electrode (17) which branches to a first branch part (17a) and a second branch part (17b), either one of an input electrode (15) and an output electrode (18) that are disposed between a first branch part (17a) and a second branch part (17b), and other one of an input electrode (15) and an output electrode (18) that are disposed outside of a first branch part (17a) and a second branch part (17b).Type: GrantFiled: January 14, 2014Date of Patent: December 12, 2017Assignee: SHARP KABUSHIKI KAISHAInventors: Takahiro Yamaguchi, Yuhichiroh Murakami, Yasushi Sasaki
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Patent number: 9798189Abstract: Provided is a liquid crystal display device that has excellent visibility while using a protective film comprising a polyester film. The liquid crystal display device comprises a backlight light source, and a liquid crystal cell disposed between two polarizers; the backlight light source being a white light-emitting diode; each of the polarizers comprising a polarizing film and protective films laminated on both sides of the polarizing film; and at least one of the protective films being a polyester film having a retardation of 3,000 to 30,000 nm.Type: GrantFiled: June 20, 2011Date of Patent: October 24, 2017Assignee: Toyobo Co., Ltd.Inventors: Koichi Murata, Yasushi Sasaki
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Patent number: 9798408Abstract: The electronic device 1 includes a press detection unit 40 configured to detect a press and a control unit 10 configured to control, when a standard for data based on press is set, such that a parameter value associated with a predetermined process is increased/decreased, according to a difference between the standard and the data based on press detected by the press detection unit 40, thus portions operated by an operator can be reduced and operation steps by the operator can be reduced as well.Type: GrantFiled: May 25, 2012Date of Patent: October 24, 2017Assignee: KYOCERA CorporationInventors: Yumiko Kashiwa, Yasushi Sasaki, Makoto Chishima, Takashi Yamada
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Publication number: 20170261794Abstract: Provided is a liquid crystal display device that has excellent visibility while using a protective film comprising a polyester film. The liquid crystal display device comprises a backlight light source, and a liquid crystal cell disposed between two polarizers; the backlight light source being a white light-emitting diode; each of the polarizers comprising a polarizing film and protective films laminated on both sides of the polarizing film; and at least one of the protective films being a polyester film having a retardation of 3,000 to 30,000 nm.Type: ApplicationFiled: March 31, 2017Publication date: September 14, 2017Applicant: Toyobo Co., Ltd.Inventors: Koichi MURATA, Yasushi SASAKI
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Patent number: 9755431Abstract: A power management system has power supplying means, measuring means that measures power generation environment for the power supplying means, and communication means that transmits information measured by the measuring means. The power management system comprises: a control unit that controls the measuring means and the communication means. The power supplying means is used as a power source for the measuring means and the communication means. The control unit sets a first power threshold to be used for determining whether or not to switch operation states of the measuring means and a second power threshold to be used for determining whether or not to switch operation states of the communication means on the basis of a power supply that is supplied from the power supplying means.Type: GrantFiled: March 23, 2012Date of Patent: September 5, 2017Assignee: KYOCERA CORPORATIONInventors: Yasushi Sasaki, Nobuo Kuchiki, Takashi Baba, Mitsuhiro Kitaji
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Patent number: 9740286Abstract: In order to enable an operator to unfailingly recognize a retrieved character string displayed on a display unit as a result of retrieval from a target such as text, a character string retrieval apparatus 1 for retrieving the character string from the target includes a display unit 20 for displaying a retrieval result of the character string, an operation unit 30 for detecting an input operation, a tactile sensation providing unit 40 for vibrating the operation unit 30, and a control unit 10 for shifting an area of the retrieval result of the character string displayed on the display unit 20, based on the input operation detected by the operation unit 30, and, when displaying the retrieved character string on the display unit 20, for controlling the tactile sensation providing unit 40 such that a tactile sensation is provided to an object pressing the operation unit 30.Type: GrantFiled: August 18, 2011Date of Patent: August 22, 2017Assignee: KYOCERA CorporationInventor: Yasushi Sasaki
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Patent number: 9715940Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A set transistor Tr2 switches between whether or not to provide an output of an on-potential output unit 2 to a gate terminal of Tr1 in accordance with an output of a set control unit 3. The set control unit 3 controls a gate terminal of Tr2 into a floating state in part of a period during which a high-level potential is provided to the gate terminal of Tr1. The gate potential of Tr2 is raised by being pushed up, whereby a high-level potential without a threshold drop is provided to the gate terminal of Tr1, and rounding of an output signal OUT is decreased when the output signal OUT shifts to a high level. Accordingly, an operation margin with respect to fluctuation of a threshold voltage of the transistor is increased.Type: GrantFiled: February 17, 2014Date of Patent: July 25, 2017Assignee: SHARP KABUSHIKI KAISHAInventors: Yuhichiroh Murakami, Yasushi Sasaki, Shige Furuta, Shuji Nishi, Makoto Yokoyama
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Patent number: 9711238Abstract: The purpose of the present invention is to reduce a circuit size of a shift register. A shift register of the present invention includes stages each including a holding circuit (11) and a clock output circuit (12). The clock output circuit (12) includes an output terminal (O) that outputs a signal having a high electric potential or a low electric potential, depending on at least one of outputs (Q) from the holding circuit (11) and on a second clock signal. The holding circuit (11) carries out a reset operation in accordance with a first clock signal supplied to a transistor (N1).Type: GrantFiled: December 10, 2012Date of Patent: July 18, 2017Assignee: SHARP KABUSHIKI KAISHAInventors: Yuhichiroh Murakami, Yasushi Sasaki, Takahiro Yamaguchi