Abstract: Provided is a shift register capable of being driven using various clock signals, with low power consumption. A bistable circuit of a shift register is provided with first to third transistors, first to third input terminals, and an output terminal. In the first transistor, a gate terminal thereof and a first conduction terminal thereof are connected to the first input terminal. In the second transistor, a gate terminal thereof is connected to the third input terminal, and a first conduction terminal thereof is connected to the first input terminal. In the third transistor, a gate terminal thereof is connected respectively to second conduction terminals of the first and second transistors, a first conduction terminal thereof is connected to the second input terminal, and a second conduction terminal thereof is connected to the output terminal.

Abstract: An objective of the present invention is to provide a display device capable of suppressing consumption of the current flowing through gate clock signal bus lines by reducing the loads on the gate clock signal bus lines. In a shift register, which writes the voltages of a plurality of gate clock signals (CK1 to CK3) to gate bus lines (GL) via buffer circuits (BF), a plurality of gate clock signal bus lines (51a to 54a) are formed in an area between a display portion (600) and the buffer circuits (BF), independently of a clear signal bus line and other lines, so as to be adjacent to the buffer circuits (BF). This results in no area in which clear signal branch lines (61b) cross the gate clock signal bus lines (51a to 54a) and wiring lines in bistable circuits SR. Thus, it is possible to eliminate interlayer capacitance due to the crossings of the lines and fringe capacitance between the lines.

Abstract: A memory-type liquid crystal display device includes transistors (N1, N2), retention electrodes (MRY), refresh output control sections (RS1), and capacitors (Cb1). In a data retention period, an electric potential of each of the retention electrodes (MRY) is changed via a corresponding one of the capacitors (Cb1) by changing an electric potential level of a retention capacitor wire signal that is supplied to a corresponding CS line (CSL(i)). Each of the refresh output control sections (RS1) receives the electric potential thus changed of a corresponding one of the retention electrodes (MRY) via the input section and controls an electric potential of a corresponding pixel electrode (PIX) in accordance with the electric potential thus changed.

Abstract: A semiconductor device (10) provided with at least a plurality of transistors and bootstrap capacitors (Ca1 and Cb1), the semiconductor device (10) includes: a semiconductor layer (22) made of the same material as a channel layer of each of the transistors; a capacitor electrode (24) formed in an upper layer of the semiconductor layer (22); and a clock signal line (17) formed in an upper layer of the capacitor electrode (24), the capacitor electrode (24) being connected to a gate electrode of each of the transistors, the clock signal line (17) being supplied with a clock signal (CK) from outside the semiconductor device (10), the capacitors (Ca1 and Cb1) each being formed in an overlap section where the semiconductor layer (22), the gate insulating film (23) and the capacitor electrode (24) overlap one another, the overlap section and the clock signal line (17) overlapping each other when viewed from above.

Abstract: Provided is a shift register of a display-driving circuit which carries out simultaneous selection of a plurality of signal lines by using a simultaneous selection signal. A stage of the shift register includes (i) a set-reset type flip-flop and (ii) a signal generating circuit which generates an output signal of the stage by selectively outputting a signal in response to an output of the flip-flop. The output signal of the stage (i) becomes active due to an activation of the simultaneous selection signal and then (ii) remains active while the simultaneous selection is being performed, and the output from the flip-flop is inactive during a period in which a setting signal and a resetting signal are both being active. This makes it possible to quickly carry out the simultaneous selection of all the signal lines and the initialization of the shift register.

Abstract: Disclosed is a shift register for use in a display driving circuit that simultaneously selects signal lines, including, in a stage thereof: a flip-flop including an initialization terminal; and a signal generating circuit that receives a simultaneous selection signal and that generates an output signal of the stage by use of an output of the flip-flop, wherein: the output signal of the stage becomes active due to an activation of the simultaneous selection signal so as to be active during a period of the simultaneous selection; the output of the flip-flop is non-active while the initialization terminal, a set terminal, and a reset terminal of the flip-flop; and the initialization terminal of the flip-flop receives the simultaneous selection signal. This shift register makes it possible to downsize various drivers.

Abstract: A transistor circuit includes at least one transistor, wherein at least part of a connecting portion that connects the transistor (Tr1) and a power supply line (33) is formed from a material of which a channel of the transistor (Tr1) is made. This configuration reduces a circuit area of the transistor circuit.

Abstract: A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off.

Abstract: A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.

Abstract: A method for manufacturing a steel plate provided with a layered structure. A method for manufacturing a steel plate includes: i) providing a high carbon steel plate; ii) homogenizing the high carbon steel plate; iii) transforming the high carbon steel plate into an austenitic phase by heating the high carbon steel plate; iv) contacting the high carbon steel plate with an oxidization gas and converting the high carbon steel plate into a steel plate comprising surface layers that are spaced apart from each other and are decarburized to be transformed into a ferritic phase, and a center layer that is located between the surface layers and is not decarburized; and v) cooling the high carbon steel plate and transforming the center layer into a martensitic phase.

Abstract: A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.

Abstract: A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetting signal are active or inactive, as long as the initialization signal is active. The initialization signal becomes active before the end of the simultaneous selection, and then becomes inactive after the end of the simultaneous selection. This makes it possible to stabilize operation of the shift register after the end of simultaneous selection of a plurality of signal lines carried out by the display driving circuit at a predetermined timing.

Abstract: A display driving circuit for driving a liquid crystal display panel includes a shift register including a plurality of shift register circuits provided in such a way as to correspond to a plurality of gate lines, respectively, the display driving circuit having latch circuits provided in such a way as to correspond one-by-one to the shift register circuits, a polarity signal being inputted to the latch circuits. When a internal signal generated by a shift register circuit becomes active, a latch circuit loads and retains the polarity signal, and an output from the latch circuit is supplied to a CS bus line. The internal signal becomes active before a first vertical scanning period of a display picture.

Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.

Abstract: The purpose of the present invention is to achieve a display device capable of performing an all-selecting drive for gate bus lines without increasing the number of circuit elements more than heretofore and without lowering withstand voltage reliability. In a stage constituent circuit, which constitutes a shift register in a gate driver, an all-selecting signal (ALL-ON) for simultaneously turning all of gate bus lines to a selected state is given, as a low-potential power supply, to a source terminal of a thin film transistor (Tr4) for setting, at a low level, a QB node provided for setting a scanning signal (OUT) at the low level and to a source terminal of a thin film transistor (Tr3) for setting, at the low level, a Q node provided for setting the scanning signal (OUT) at a high level.

Abstract: A signal processing circuit of the present invention includes: a first input terminal; a second input terminal; a third input terminal; a first node; a second node; an output terminal; a resistor; a first signal generating section which (i) is connected to the first node, a third input terminal, and the output terminal and (ii) includes a bootstrap capacitor; and a second signal generating section which is connected to the second node, a first power supply, and the output terminal. The first node becomes active in a case where the first input terminal becomes active. The second node becomes active in a case where the second input terminal becomes active. The output terminal is connected to the first power supply via the resistor. With the configuration, it is possible to have an improvement in operational stability of the signal processing circuit.

Abstract: A flip-flop of the present invention includes: an input terminal; an output terminal; a first control signal terminal and a second control signal terminal; a first output section including a bootstrap capacitor, the first output section being connected to the first control signal terminal and the output terminal; a second output section connected to a first output section source and the output terminal; a first input section connected to the input terminal, the first input section charging the bootstrap capacitor; a discharge section discharging the bootstrap capacitor; a second input section connected to the input terminal, the second input section being also connected to the second output section; a reset section controlling the discharge section and the second output section, the reset section being connected to the second control signal terminal; a first initialization section controlling the first output section; a second initialization section controlling the first input section; and a third initializat

Abstract: In an active matrix display apparatus including: pixels provided in a matrix pattern, the pixels each including a memory circuit which retains data while refreshing the data, a data signal electric potential which is supplied from a source line in a period t1 and written to a node which is connected to a liquid capacitor is higher than a data electric potential of the node, the data electric potential being obtained in a period t14 after a refresh operation of the memory circuit.

Abstract: A display driving circuit that carries out CC driving is configured such that retaining circuits are provided in such a way as to correspond one-by-one to their respective stages of a shift register, that a polarity signal CMI is inputted to each of the latch circuits, that when an internal signal Mn generated by a shift register at the nth stage becomes active, a latch circuit corresponding to the nth stage loads and retains the polarity signal CMI, that an output signal SRBOn from the shift register at the nth stage is supplied as a scanning signal to a gate line connected to pixels corresponding to the (n+1)th stage, and that an output from latch circuit corresponding to the nth stage is supplied as CSOUTn to a CS bus line forming capacitors with pixel electrodes of pixels corresponding to the nth stage.

Abstract: Provided is an input apparatus capable of handling operation mistakes (erroneous operations) unintentionally performed by a user. An input apparatus 10 has a display unit 32 configured to display objects of folders arranged in a hierarchical structure, an input unit 34 configured to receive a pressing input to the display unit 32, a load detection unit 40 configured to detect a pressure load on the input unit 34, and a control unit 20, if the load detection unit 40 continuously detects a pressure load satisfying a first load standard for a predetermined period while the display unit 32 is displaying an object of an open folder and the input unit 34 is receiving the pressing input at a position corresponding to an object of another folder different from the open folder, configured to control to open the another folder.