Abstract: Provided is an input apparatus capable of handling operation mistakes (erroneous operations) unintentionally performed by a user. An input apparatus 10 has a display unit 32 configured to display objects of folders arranged in a hierarchical structure, an input unit 34 configured to receive a pressing input to the display unit 32, a load detection unit 40 configured to detect a pressure load on the input unit 34, and a control unit 20, if the load detection unit 40 continuously detects a pressure load not satisfying a predetermined load standard for a predetermined period after satisfying the predetermined load standard while the display unit 32 is displaying objects of open folders, configured to control to close a lowest folder among the open folders.

Abstract: The purpose of the present invention is to reduce a circuit size of a shift register. A shift register of the present invention includes stages each including a holding circuit (11) and a clock output circuit (12). The clock output circuit (12) includes an output terminal (O) that outputs a signal having a high electric potential or a low electric potential, depending on at least one of outputs (Q) from the holding circuit (11) and on a second clock signal. The holding circuit (11) carries out a reset operation in accordance with a first clock signal supplied to a transistor (N1).

Abstract: A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.

Abstract: A transistor (N1) has a gate terminal connected to a word line (Xi(1)) and a first conduction terminal connected to a bit line (Yj). A transistor (N2) has a gate terminal connected to the word line (Xi(2)) and a first conduction terminal connected to a node (PIX). A transistor (N3) has a gate terminal connected to a node (MRY) and a first conduction terminal connected to the word line (Xi(2)). A transistor (N4) has a gate terminal connected to the word line (Xi(3)), a first conduction terminal connected to a second conduction terminal of the transistor (N3), and a second conduction terminal connected to the node (PIX). Capacitors (Ca1), (Cb1), (Cap1) are formed between the node (PIX) and a reference electric potential wire (RL1), between the node (MRY) and the reference electric potential wire (RL1), and between the first conduction terminal of the transistor (N3) and the node (MRY), respectively.

Abstract: A memory liquid crystal display device includes a transistor (N1), a transistor (N2), a transistor (N3), a transistor (N4), a first storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37a and a CS line CSL(i)) connected to a pixel electrode (7), and a second storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37b and a CS extension section 10bb) connected to the pixel electrode (7) via the transistor (N2), the pixel electrode (7) being connected to (a) a source line (SL(j)) via the transistor (N1), (b) a data transfer control line (DT(i)) via the transistor (N4) and the third transistor, (c) a drain electrode (9a) of the transistor (N1) via a contact hole (13), and (d) a source electrode (8b) of the transistor (N2) and to a drain electrode (9c) of the transistor (N4), via a contact hole (14).

Abstract: A power transducer is downsized by reducing the size of a power source board and highly reliable. The power source board is provided in the power transducer and for a large-current circuit. The power transducer includes a power semiconductor module having lead terminals. Of the lead terminals provided for the power semiconductor module and connected with the main circuit board, predetermined one or ones of the lead terminals is or are connected with the main circuit board in the vicinity of a main circuit terminal stage and at a position or positions lower than the main circuit terminal stage. Alternatively, predetermined one or ones of the lead terminals is or are connected with the main circuit board at a position or positions lower than a position at which the main circuit terminal stage is provided.

Abstract: In a memory liquid crystal display device, a potential of a storage capacitor line signal (CS) supplied to the CS lines (CSL(i)) are once decreased (?Vcs) while the gate lines (GL(i)) are made simultaneously active (period t4, period t10) in the data holding period (T2), and the potential of the storage capacitor line signal (CS) is made back to its original potential while the gate lines (GL(i)) are made simultaneously inactive and the refresh output control lines (RC(i)) are made active (period t5, period t11). This reduces flicker, thereby allowing for improvement in display quality of the memory liquid crystal display device.

Abstract: A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; and an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal, the electric charge control section and the first output section being connected to each other via a relay section for either electrically connecting the electric charge control section and the first output section to each other or electrically blocking the electric charge control section and the first output section from each other, the electric charge control section including a resistor connected to a second power source.

Abstract: A memory device can perform a first operation mode in which a discrete level is supplied to cause the memory cell to retain a logical level, and prevent unnecessary power consumption due to an operation of a power source which is unnecessary in the first operation mode. The memory device includes: a first power source for supplying a first potential level; a second power source for supplying a second potential level, a third power source for supplying a potential higher than a highest potential of discrete levels; and a fourth power source for supplying a potential lower than a lowest potential of the discrete levels, the first and second potential levels being used to supply the discrete levels, when the first operation is carried out, VDD, VSS, and GVDD being caused to be in operation and the fourth power source being stopped from being in operation.

Abstract: Provided are a display device capable of preventing image noise arising from changes in potential of a common electrode and auxiliary capacitor lines at the time of a switch between a normal mode and a memory mode and a method for driving such a display device. In a case where it is necessary to cause the common electrode and the auxiliary capacitor lines to change in potential along with a switch between the normal mode and the memory mode, the change in potential is made while electrically connecting a node of each memory circuit to a corresponding source line with the corresponding source line having its potential fixed and with the memory circuit having its a switch circuit in a conductive state.

Abstract: In one embodiment of the present invention, on each source bus line, an electric charge escaping transistor is provided having the same polarity as a pixel transistor and having a gate to which a turn-off voltage signal of the pixel transistor is supplied. When an active matrix liquid crystal display device is powered off, the turn-off voltage signal is made to reach the GND level before a turn-on voltage signal of the pixel transistor reaches the GND level, so that the pixel transistor and the electric charge escaping transistor are made half-open. This lets electric charges accumulated in the pixel escape to a common electrode TCOM.

Abstract: The invention provides a method for efficiently improving emulsifying ability of gum arabic, in other words, a method for producing gum arabic with excellent emulsifying ability. Further, the present invention provides a method by which a gum arabic modified so as to have a high emulsifying ability can be obtained without involving the problem of forming syrupy masses or sticking to the vessel or the trouble of excessive dehydration or charring. The above-described methods can be carried out by heating gum arabic (unmodified) under dry conditions. Preferably, the method is carried out by heating gum arabic in such a manner that the loss-on-drying is not more than 3%.

Abstract: A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal.

Abstract: A memory-type liquid crystal display device includes a liquid crystal panel including memory circuits, and conducts a refresh operation more than once during a display holding period after rewriting of a screen. The memory-type liquid crystal display device increases at least one of (i) a frequency at which the screen is rewritten and (ii) a frequency at which the refresh operation is conducted during the display holding period as an intensity of light received by the liquid crystal panel increases. This allows the memory-type liquid crystal display device to reduce power consumption while keeping its display quality.

Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.

Abstract: The electronic device 1 includes a press detection unit 40 configured to detect a press and a control unit 10 configured to control, when a standard for data based on press is set, such that a parameter value associated with a predetermined process is increased/decreased, according to a difference between the standard and the data based on press detected by the press detection unit 40, thus portions operated by an operator can be reduced and operation steps by the operator can be reduced as well.

Abstract: The invention provides a liquid crystal display device, as well as a polarizer and a protective film suitable for the liquid crystal display device. The liquid crystal display device comprises a backlight light source, two polarizers, and a liquid crystal cell disposed between the two polarizers; the backlight light source being a white light-emitting diode light source; each of the two polarizers comprising a polarizing film and protective films laminated on both sides of the polarizing film; at least one of the protective films being a polyester film having an adhesion-facilitating layer; the polyester film having a retardation of 3,000 to 30,000 nm; and the adhesion-facilitating layer comprising a polyester resin (A) and a polyvinyl alcohol resin (B).

Abstract: This invention relates to an agent, a composition and a product comprising at least one apoptosis-inducing substance, and at least one substance which inhibits expression and/or activity of an apoptosis-inhibiting substance; a method for inducing apoptosis or for treating a proliferative disease using one or more of them; a nucleic acid construct comprising a nucleic acid molecule encoding a protein to be expressed and a nucleic acid molecule which inhibits expression of an undesired protein; and a method for expressing a desired protein in a cell while inhibiting the expression of an undesired protein.

Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.

Abstract: An object of the present invention is to provide a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. In a booster section (11a), capacitors (C1) and (C2) have their respective first terminals connected with transistors (Q1, Q3) and (Q2, Q4) respectively. Each transistor has its gate terminal supplied with control signals generated in a driver section (11b). The driver section (11b) includes capacitors (C3, C4) connected with input terminals (Ti3, Ti4) for respective supply of clock signals DCK2, DCK2B each having a voltage alternating between ?VDD and VDD (VDD represents an input supply voltage from outside), as level-shifted signals of clock signals DCK1, DCK1B which are supplied to second terminals of the capacitors (C1, C2) respectively.