Patents by Inventor Yasushi Sasaki
Yasushi Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7897229Abstract: A pressure-sensitive adhesive article 100 includes a release sheet 1 constituted from a releasing agent layer 11 and a base material 12, and a pressure-sensitive adhesive sheet 2 constituted from a pressure-sensitive adhesive layer 21 and a pressure-sensitive adhesive sheet base 22. Such a pressure-sensitive adhesive article 100 has a structure in which the pressure-sensitive adhesive sheet 2 is laminated on the release sheet 1 so that the pressure-sensitive adhesive layer 21 is in contact with the releasing agent layer 11. The releasing agent layer 11 is composed of a material containing substantially no silicone compound. The releasing agent layer 11 is mainly composed of an elastomer and has a Young's modulus of 1.5 GPa or less. Preferred examples of the elastomer include polybutadiene rubber (especially, 1,4-polybutadiene rubber), polyisoprene rubber, and ethylene propylene rubber. The release sheet 1 has excellent releasability and has little adverse effect on electric components and the like.Type: GrantFiled: March 21, 2006Date of Patent: March 1, 2011Assignee: Lintec CorporationInventors: Daisuke Tomita, Yasushi Sasaki, Takuo Nishida
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Publication number: 20100329532Abstract: An X-ray inspecting apparatus capable of high-speed inspection of a prescribed inspection area of an object of inspection is provided. The X-ray inspecting apparatus includes: a scanning X-ray source for outputting X-ray; an X-ray detector driving unit on which a plurality of X-ray detectors are mounted, and capable of driving the plurality of X-ray detectors independently; and an image acquisition control mechanism controlling acquisition of image data by X-ray detector driving unit and X-ray detectors. A scanning X-ray source emits X-ray while moving the X-ray focal point of the X-ray source to each of X-ray emission originating positions set for each X-ray detector such that the X-ray passes through a prescribed inspection area of an object of inspection and enters each X-ray detector. Image pick-up by some of the X-ray detectors and movement of other X-ray detectors to an image pick-up position are executed in parallel and alternately.Type: ApplicationFiled: December 25, 2008Publication date: December 30, 2010Inventors: Masayuki Masuda, Noriyuki Kato, Shinji Sugita, Tsuyoshi Matsunami, Yasushi Sasaki
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Publication number: 20100309184Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.Type: ApplicationFiled: August 20, 2008Publication date: December 9, 2010Inventors: Etsuo Yamamoto, Yasushi Sasaki, Yuhichiroh Murakami, Shige Furuta
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Publication number: 20100259529Abstract: An embodiment of the present invention provides a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. When a boosted voltage is obtained at a first terminal of a first capacitor in a booster section, a booster control section supplies this boosted voltage to a third capacitor, to boost the voltage further thereby turning ON a first transistor. When a boosted voltage is obtained at a first terminal of a second capacitor in the booster section, the booster control section supplies this boosted voltage to a fourth capacitor, to boost the voltage further thereby turning ON a second transistor. This arrangement eliminates a problem of voltage drop by threshold value in the first and the second transistors which serve as output-side switching elements.Type: ApplicationFiled: September 1, 2008Publication date: October 14, 2010Inventors: Shuji Nishi, Sachio Tsujino, Yuhichiroh Murakami, Yasushi Sasaki, Seijirou Gyouten
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Publication number: 20100259525Abstract: At least one embodiment of the present invention is directed to, even when external noise is applied to a shift register during all-on operation, preventing through-current from flowing in unit circuits and also to prevent increase in load on all-on control signal lines. When a high-level all-on control signal is provided to a unit circuit of a shift register, a transistor T3 is brought into off-state, so that a transistor T2 cannot output an on-voltage to a first output terminal. However, a transistor T24 is brought into on-state, so, that the first output terminal outputs an on-voltage to the exterior. On the other hand, a transistor T32 is brought into on-state, so that a second output terminal outputs an off-voltage to a unit circuit 11 in the next stage. At this time, the transistor T3 is kept in off-state, so that no through-current flows to the transistors T24 and T3. At least one embodiment of the present invention is suitable for driver circuits or suchlike of display devices and imaging devices.Type: ApplicationFiled: August 18, 2008Publication date: October 14, 2010Inventors: Hiroyuki Ohkawa, Shige Furuta, Yasushi Sasaki, Yuhichiroh Murakami
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Publication number: 20100253393Abstract: A single-phase input including transistors all of which have only a single type of channel polarity, which buffer includes: a buffer section 32, including a first series circuit formed by two n-channel transistors connected to each other in series, a second series circuit formed by two n-channel transistors connected to each other in series at a connection point OUT, and a capacitor; and an inverted-signal generating section for generating an inverted-signal from an input signal, the inverted-signal generating section including n-channel transistors but no p-channel transistor, the input signal being inputted to respective gates of the transistors, the inverted-signal being inputted to a gate of the transistor 4, and an output signal being outputted via the connection point OUT. With the buffer, it is possible that a consumption current be reduced and a current drive for a load is enhanced.Type: ApplicationFiled: August 19, 2008Publication date: October 7, 2010Applicant: Sharp Kabushiki KaishaInventors: Etsuo Yamamoto, Yuhichiro Murakami, Yasushi Sasaki, Seijirou Gyouten, Shinsaku Shimizu
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Publication number: 20100245328Abstract: In a storage capacitor line drive circuit driving a storage capacitor line of an active-matrix display device and driven by outputs of a scanning signal line drive circuit, at least one (VSS) of a high-potential supply voltage (VDD) and a low-potential supply voltage (VSS) differs from a supply voltage (GVSS) of a corresponding logical level of the scanning signal line drive circuit, the high-potential supply voltage and the low-potential supply voltage being used for generating a signal voltage of a preceding stage to an output stage. This makes it possible to achieve a storage capacitor line drive circuit capable of avoiding malfunctioning even in a case where the storage capacitor line drive circuit receives noise from a scanning signal line, and a display device including the storage capacitor line drive circuit.Type: ApplicationFiled: August 21, 2008Publication date: September 30, 2010Inventors: Yasushi Sasaki, Yuhichiroh Murakami, Makoto Yokoyama, Shige Furuta
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Publication number: 20100245305Abstract: A display driving circuit of the present invention includes: a source driver (20) which outputs a source signal; a gate driver (30) which outputs a gate signal for turning on a switching element on a row; and a CS driver (40) which outputs a CS signal (CSOUT) whose electric potential is switched in a predetermined direction (low to high or high to low) in accordance with a polarity of the source signal. A CS driver (CSn) on an n-th row outputs a CS signal (CSOUT) to the n-th row in accordance with a gate signal (GLn) for the n-th row outputted from a gate driver (Gn) provided on the n-th row. This makes it possible to provide a display driving circuit which enables CC driving with a simple configuration.Type: ApplicationFiled: September 2, 2008Publication date: September 30, 2010Inventors: Makoto Yokoyama, Yasushi Sasaki, Yuhichiroh Murakami
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Publication number: 20100245327Abstract: An object of the present invention is to provide a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. In a booster section (11a), capacitors (C1) and (C2) have their respective first terminals connected with transistors (Q1, Q3) and (Q2, Q4) respectively. Each transistor has its gate terminal supplied with control signals generated in a driver section (11b). The driver section (11b) includes capacitors (C3, C4) connected with input terminals (Ti3, Ti4) for respective supply of clock signals DCK2, DCK2B each having a voltage alternating between ?VDD and VDD (VDD represents an input supply voltage from outside), as level-shifted signals of clock signals DCK1, DCK1B which are supplied to second terminals of the capacitors (C1, C2) respectively.Type: ApplicationFiled: July 24, 2008Publication date: September 30, 2010Applicant: SHARP KABUSHIKI KAISHAInventors: Sachio Tsujino, Shuji Nishi, Yuhichiroh Murakami, Yasushi Sasaki, Seijirou Gyouten
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Publication number: 20100244946Abstract: A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal.Type: ApplicationFiled: August 26, 2008Publication date: September 30, 2010Inventors: Yuhichiroh Murakami, Yasushi Sasaki, Shige Furuta
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Publication number: 20100214206Abstract: At least one embodiment the present invention a plurality of unit circuits connected in multiple stages, to normal operation when the unit circuits are simultaneously turned on to output high-level output signals. When a shift register malfunctions, so that output signals provided by previous- and subsequent-stage unit circuits are simultaneously set to high level, malfunction restoration circuits and included in a unit circuit detect the malfunction in at least one embodiment. The malfunction restoration circuit provides a high voltage to a node, thereby forcibly pulling down an output signal. Also, the malfunction restoration circuit forcibly discharges another node, so that a charge accumulated in a capacitance is released. As a result, the shift register in malfunction can be instantaneously restored to normal operation. At least one embodiment of the present invention is suitable for driver circuits or suchlike of display devices and imaging devices.Type: ApplicationFiled: August 26, 2008Publication date: August 26, 2010Inventors: Makoto Yokoyama, Shige Furuta, Yuhichiroh Murakami, Yasushi Sasaki
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Patent number: 7754970Abstract: A high frequency electronic part comprising a conductor wiring for transmitting an electric signal of 100 MHz to 100 GHz, and an insulation layer composed of a void containing thermoplastic resin film orientated in at least one direction by stretching. The void containing thermoplastic resin film contains voids in the range between 3% and 45% by volume, the number of voids in a thickness direction of the film is 5 or more, and a ratio of the number of voids to film thickness defined by the following equation is in the range between 0.1 and 10 voids/?m: ratio of the number of voids to film thickness (voids/?m)=the number of voids (voids) in film thickness direction/film thickness (?m).Type: GrantFiled: May 31, 2006Date of Patent: July 13, 2010Assignee: Toyo Boseki Kabushiki KaishaInventors: Yasushi Sasaki, Seiichiro Yokoyama
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Publication number: 20100141642Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.Type: ApplicationFiled: May 15, 2008Publication date: June 10, 2010Inventors: Shige Furuta, Yuhichiroh Murakami, Yasushi Sasaki, Shinsaku Shimizu
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Publication number: 20100141641Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.Type: ApplicationFiled: May 15, 2008Publication date: June 10, 2010Inventors: Shige Furuta, Yuhichiroh Murakami, Yasushi Sasaki, Shinsaku Shimizu
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Publication number: 20100128009Abstract: One embodiment of the present invention includes: a gate line drive circuit that outputs, in a horizontal scanning period which is sequentially allocated to each one of rows, a gate signal for turning on the switching element on one row; a source bus line drive circuit that outputs a source signal of which polarity is reversed in sync with the horizontal scanning period for each of the rows and of which polarity is opposite in an adjacent horizontal scanning period on one and the same row; a CS bus line drive circuit that outputs, after the horizontal scanning period for each of the rows, a CS signal of which potential is switched along a direction (from low level to high level or from high level to low level) determined according to the polarity of the source signal in the horizontal scanning period concerned, wherein the CS bus line drive circuit outputs the CS signal in a first frame so that a potential of the CS signal at a time of on-to-off switching of the switching element on the one row is different fType: ApplicationFiled: July 14, 2008Publication date: May 27, 2010Inventors: Atsushi Okada, Yasushi Sasaki
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Patent number: 7691413Abstract: The invention provides a composite particle, a process for producing the same, and cosmetics containing the same The invention relates to composite particles containing a polyolefin-based resin having a crystallization degree of 80% or less and zinc oxide and obtained by hot melt microencapsulation or spray cooling, or composite particles containing a polyolefin-based resin having a crystallization degree of 80% or less and zinc oxide, wherein the degree of remaining zinc oxide in the particles is 50 wt % or more after being dipped for 1 hour in 0.5 mol/L hydrochloric acid solution at 25° C. (solution composition: water and ethanol in equal volumes), a process for producing the composite particles, and cosmetics containing the composite particles.Type: GrantFiled: September 22, 2005Date of Patent: April 6, 2010Assignee: Kao CorporationInventors: Masafumi Miyamoto, Yasushi Sasaki, Toshiya Shimada, Shinobu Hiramatsu
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Publication number: 20100079956Abstract: A power transducer is downsized by reducing the size of a power source board and highly reliable. The power source board is provided in the power transducer and for a large-current circuit. The power transducer includes a power semiconductor module having lead terminals. Of the lead terminals provided for the power semiconductor module and connected with the main circuit board, predetermined one or ones of the lead terminals is or are connected with the main circuit board in the vicinity of a main circuit terminal stage and at a position or positions lower than the main circuit terminal stage. Alternatively, predetermined one or ones of the lead terminals is or are connected with the main circuit board at a position or positions lower than a position at which the main circuit terminal stage is provided.Type: ApplicationFiled: August 7, 2009Publication date: April 1, 2010Applicant: HITACHI INDUSTRIAL EQUIPMENT SYSTEMS CO., LTD.Inventors: Satoshi IBORI, Yasushi SASAKI, Yutaka MAENO, Masayuki HIROTA, Kazuyuki FUKUSHIMA
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Patent number: 7665727Abstract: A system, method, and process of for packaging liquid product into cartons using an automated packaging system and more specifically methods of enclosing the packaging system and routing conditioned air over the cartons is presented. More specifically, a carton magazine assembly for collecting plastic coated paper carton blanks prior to sanitization, assembly, filling, and sealing includes a magazine cover that can be opened to insert additional carton blanks into the packaging system as necessary. The magazine cover has an integrated air manifold that directs pressurized conditioned air over the carton blanks towards suction ports. The suction ports collect the air with potential contaminants and the filters the air prior to ejecting it away from the vicinity of the packaging system.Type: GrantFiled: December 15, 2005Date of Patent: February 23, 2010Assignee: Evergreen Packaging Inc.Inventors: Gerald Paul Berger, Cletus Emerich Kreher, Yasushi Sasaki, Toshiyuki Kanemaru
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Publication number: 20090297860Abstract: A light diffusion film which has excellent light transmittance and light diffusibility while maintaining excellent heat resistance, mechanical strength and thickness accuracy intrinsic to a biaxially stretched film, and is suppressed in generation of curling after heat treatment, is provided. A light diffusion film consisting of a biaxially stretched laminated film having a supporting layer consisting of a crystalline polyester, and a light diffusion layer laminated on at least one side of the supporting layer by a co-extrusion method, wherein the light diffusion layer comprises 60 to 98 parts by mass of the crystalline polyester and 2 to 40 parts by mass of a light diffusion additive incompatible with the polyester, and the light diffusion film has a planar orientation degree (?P) of 0.080 to 0.160, a total light transmittance of 85% or more, and a haze of 30% or more.Type: ApplicationFiled: March 29, 2007Publication date: December 3, 2009Applicant: TOYO BOSEKI KABUSHIKI KAISHAInventors: Yasushi Sasaki, Yoshitomo Ikehata, Jun Inagaki
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Publication number: 20090149025Abstract: A remover composition containing 1,3-propanediamine (a), 1-hydroxyethylidene-1,1-diphosphonic acid (b) and water, wherein the remover composition contains the component (a) in an amount of from 0.2 to 30% by weight, the component (b) in an amount of from 0.05 to 10% by weight, and the water in an amount of from 60 to 99.75% by weight, and wherein the composition has a pH at 20° C. of from 9 to 13; and a remover composition containing an organic amine (A), an organic phosphonic acid (B), a linear sugar alcohol (C) and water, wherein the remover composition contains the component (A) in an amount of from 0.2 to 30% by weight, the component (B) in an amount of from 0.05 to 10% by weight, the component (C) in an amount of from 0.1 to 10% by weight, and the water in an amount of from 50 to 99.65% by weight, and wherein the composition has a pH at 20° C. of from 9 to 13.Type: ApplicationFiled: June 5, 2006Publication date: June 11, 2009Inventors: Sadaharu Miyamoto, Yasushi Sasaki