Abstract: A single-phase input including transistors all of which have only a single type of channel polarity, which buffer includes: a buffer section 32, including a first series circuit formed by two n-channel transistors connected to each other in series, a second series circuit formed by two n-channel transistors connected to each other in series at a connection point OUT, and a capacitor; and an inverted-signal generating section for generating an inverted-signal from an input signal, the inverted-signal generating section including n-channel transistors but no p-channel transistor, the input signal being inputted to respective gates of the transistors, the inverted-signal being inputted to a gate of the transistor 4, and an output signal being outputted via the connection point OUT. With the buffer, it is possible that a consumption current be reduced and a current drive for a load is enhanced.

Abstract: A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal.

Abstract: An X-ray inspecting apparatus capable of high-speed inspection of a prescribed inspection area of an object of inspection is provided. The X-ray inspecting apparatus includes: a scanning X-ray source for outputting X-ray; an X-ray detector driving unit on which a plurality of X-ray detectors are mounted, and capable of driving the plurality of X-ray detectors independently; and an image acquisition control mechanism controlling acquisition of image data by X-ray detector driving unit and X-ray detectors. A scanning X-ray source emits X-ray while moving the X-ray focal point of the X-ray source to each of X-ray emission originating positions set for each X-ray detector such that the X-ray passes through a prescribed inspection area of an object of inspection and enters each X-ray detector. Image pick-up by some of the X-ray detectors and movement of other X-ray detectors to an image pick-up position are executed in parallel and alternately.

Abstract: A power transducer is downsized by reducing the size of a power source board and highly reliable. The power source board is provided in the power transducer and for a large-current circuit. The power transducer includes a power semiconductor module having lead terminals. Of the lead terminals provided for the power semiconductor module and connected with the main circuit board, predetermined one or ones of the lead terminals is or are connected with the main circuit board in the vicinity of a main circuit terminal stage and at a position or positions lower than the main circuit terminal stage. Alternatively, predetermined one or ones of the lead terminals is or are connected with the main circuit board at a position or positions lower than a position at which the main circuit terminal stage is provided.

Abstract: A method for manufacturing a steel plate provided with a layered structure. A method for manufacturing a steel plate includes: i) providing a high carbon steel plate; ii) homogenizing the high carbon steel plate; iii) transforming the high carbon steel plate into an austenitic phase by heating the high carbon steel plate; iv) contacting the high carbon steel plate with an oxidization gas and converting the high carbon steel plate into a steel plate comprising surface layers that are spaced apart from each other and are decarburized to be transformed into a ferritic phase, and a center layer that is located between the surface layers and is not decarburized; and v) cooling the high carbon steel plate and transforming the center layer into a martensitic phase.

Abstract: A steel sheet which is decarburized after being strip casted and a method for manufacturing the same are provided. A method for manufacturing the steel sheet includes i) providing molten iron, ii) removing sulfur, phosphorus, and silicon from the molten iron, iii) strip casting the molten iron and providing the steel sheet, and iv) heating and contacting the steel sheet with an oxidization gas while decarburizing the steel sheet.

Abstract: A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.

Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.

Abstract: An embodiment of the present invention provides a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. When a boosted voltage is obtained at a first terminal of a first capacitor in a booster section, a booster control section supplies this boosted voltage to a third capacitor, to boost the voltage further thereby turning ON a first transistor. When a boosted voltage is obtained at a first terminal of a second capacitor in the booster section, the booster control section supplies this boosted voltage to a fourth capacitor, to boost the voltage further thereby turning ON a second transistor. This arrangement eliminates a problem of voltage drop by threshold value in the first and the second transistors which serve as output-side switching elements.

Abstract: One embodiment of the present invention includes: a gate line drive circuit that outputs, in a horizontal scanning period which is sequentially allocated to each one of rows, a gate signal for turning on the switching element on one row; a source bus line drive circuit that outputs a source signal of which polarity is reversed in sync with the horizontal scanning period for each of the rows and of which polarity is opposite in an adjacent horizontal scanning period on one and the same row; a CS bus line drive circuit that outputs, after the horizontal scanning period for each of the rows, a CS signal of which potential is switched along a direction (from low level to high level or from high level to low level) determined according to the polarity of the source signal in the horizontal scanning period concerned, wherein the CS bus line drive circuit outputs the CS signal in a first frame so that a potential of the CS signal at a time of on-to-off switching of the switching element on the one row is different f

Abstract: A one-input and three-output demultiplexer that includes sampling switches for sampling a video signal is provided at one end side of source bus lines, and a one-input and three-output demultiplexer that includes test switches provided corresponding to sampling switches and that uses a test video signal as an input signal is provided at the other end side of the source bus lines. When an any control signal out of three control signals for controlling states of a sampling switch and a test switch is defined as a target control signal, a source bus line connected to the sampling switch which is set to an on state by the target control signal and a source bus line connected to the test switch which is set to an on state by the target control signal are different.

Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.

Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.

Abstract: A light diffusion film which has excellent light transmittance and light diffusibility while maintaining excellent heat resistance, mechanical strength and thickness accuracy intrinsic to a biaxially stretched film, and is suppressed in generation of curling after heat treatment, wherein the film comprises a biaxially stretched laminated film having a supporting layer consisting of a crystalline polyester, and a light diffusion layer laminated on at least one side of the supporting layer by a co-extrusion method, wherein the light diffusion layer comprises 60 to 98 parts by mass of the crystalline polyester and 2 to 40 parts by mass of a light diffusion additive incompatible with the polyester, and the light diffusion film has a planar orientation degree (?P) of 0.080 to 0.160, a total light transmittance of 85% or more, and a haze of 30% or more.

Abstract: Provided is a display device which can prevent screen noise caused such that a potential of a common electrode is reversed after a memory mode enters from a refresh period to an entire write-in period, and a method for driving the display device. The memory mode includes (i) an entire write-in period in which a potential of the common electrode (COM) is fixed and the display data is written into all the memory circuits (node (PIX)) in each row and (ii) a refresh period in which the display data which has been written during the entire write-in period is refreshed at least once while the common electrode (COM) is driven. In the memory mode, the potential of the common electrode during the entire write-in period being a potential which the common electrode having been driven had at the end of a refresh period preceding the entire write-in period.

Abstract: [Object] The present invention relates to a turmeric pigment composition. More specifically, the present invention provides a turmeric pigment composition in which aggregation and sedimentation of a turmeric pigment over time is effectively prevented even when a concentrated amount of turmeric pigment is incorporated in a solvent; the turmeric pigment composition also ensures a desirable color-developing property, and is capable of stably adding a deep color with a bright tone, which was never accomplished by a hitherto-known colorant.

Abstract: A memory-type liquid crystal display device includes a liquid crystal panel including memory circuits, and conducts a refresh operation more than once during a display holding period after rewriting of a screen. The memory-type liquid crystal display device increases at least one of (i) a frequency at which the screen is rewritten and (ii) a frequency at which the refresh operation is conducted during the display holding period as an intensity of light received by the liquid crystal panel increases. This allows the memory-type liquid crystal display device to reduce power consumption while keeping its display quality.

Abstract: At least one embodiment of the present invention is directed to, even when external noise is applied to a shift register during all-on operation, preventing through-current from flowing in unit circuits and also to prevent increase in load on all-on control signal lines. When a high-level all-on control signal is provided to a unit circuit of a shift register, a transistor T3 is brought into off-state, so that a transistor T2 cannot output an on-voltage to a first output terminal. However, a transistor T24 is brought into on-state, so that the first output terminal outputs an on-voltage to the exterior. On the other hand, a transistor T32 is brought into on-state, so that a second output terminal outputs an off-voltage to a unit circuit 11 in the next stage. At this time, the transistor T3 is kept in off-state, so that no through-current flows to the transistors T24 and T3.

Abstract: Provided is a memory device that allows an amount of leakage into a first retaining section to which a binary logic level is written to be balanced between different circuit states. A predetermined period is set in which in a state where a first control section turns off an output element, (i) a first retaining section and a second retaining section retain an identical binary logic level, (ii) an electric potential of a voltage supply is set to one of a first electric potential level and a second electric potential level, (iii) the other one of the first electric potential level and the second electric potential level is supplied from a column driver to a fourth wire, and (iv) subsequently the fourth wire is shifted to a floating state.

Abstract: In a memory liquid crystal display device, a potential of a storage capacitor line signal (CS) supplied to the CS lines (CSL(i)) are once decreased (?Vcs) while the gate lines (GL(i)) are made simultaneously active (period t4, period t10) in the data holding period (T2), and the potential of the storage capacitor line signal (CS) is made back to its original potential while the gate lines (GL(i)) are made simultaneously inactive and the refresh output control lines (RC(i)) are made active (period t5, period t11). This reduces flicker, thereby allowing for improvement in display quality of the memory liquid crystal display device.