Abstract: A memory device can perform a first operation mode in which a discrete level is supplied to cause the memory cell to retain a logical level, and prevent unnecessary power consumption due to an operation of a power source which is unnecessary in the first operation mode. The memory device includes: a first power source (VDD) for supplying a first potential level; a second power source (VSS) for supplying a second potential level, a third power source (GVDD) for supplying a potential higher than a highest potential of discrete levels; and a fourth power source for supplying a potential lower than a lowest potential of the discrete levels, the first and second potential levels being used to supply the discrete levels, when the first operation is carried out, VDD, VSS, and GVDD being caused to be in operation and the fourth power source being stopped from being in operation.

Abstract: A memory liquid crystal display device includes a transistor (N1), a transistor (N2), a transistor (N3), a transistor (N4), a first storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37a and a CS line CSL(i)) connected to a pixel electrode (7), and a second storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37b and a CS extension section 10bb) connected to the pixel electrode (7) via the transistor (N2), the pixel electrode (7) being connected to (a) a source line (SL(j)) via the transistor (N1), (b) a data transfer control line (DT(i)) via the transistor (N4) and the third transistor, (c) a drain electrode (9a) of the transistor (N1) via a contact hole (13), and (d) a source electrode (8b) of the transistor (N2) and to a drain electrode (9c) of the transistor (N4), via a contact hole (14).

Abstract: A transistor (N1) has a gate terminal connected to a word line (Xi(1)) and a first conduction terminal connected to a bit line (Yj). A transistor (N2) has a gate terminal connected to the word line (Xi(2)) and a first conduction terminal connected to a node (PIX). A transistor (N3) has a gate terminal connected to a node (MRY) and a first conduction terminal connected to the word line (Xi(2)). A transistor (N4) has a gate terminal connected to the word line (Xi(3)), a first conduction terminal connected to a second conduction terminal of the transistor (N3), and a second conduction terminal connected to the node (PIX). Capacitors (Ca1), (Cb1), (Cap1) are formed between the node (PIX) and a reference electric potential wire (RL1), between the node (MRY) and the reference electric potential wire (RL1), and between the first conduction terminal of the transistor (N3) and the node (MRY), respectively.

Abstract: A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.

Abstract: Provided are a display device capable of preventing image noise arising from changes in potential of a common electrode and auxiliary capacitor lines at the time of a switch between a normal mode and a memory mode and a method for driving such a display device. In a case where it is necessary to cause the common electrode and the auxiliary capacitor lines to change in potential along with a switch between the normal mode and the memory mode, the change in potential is made while electrically connecting a node of each memory circuit to a corresponding source line with the corresponding source line having its potential fixed and with the memory circuit having its a switch circuit in a conductive state.

Abstract: In an active matrix display apparatus including: pixels provided in a matrix pattern, the pixels each including a memory circuit which retains data while refreshing the data, a data signal electric potential which is supplied from a source line in a period t1 and written to a node which is connected to a liquid capacitor is higher than a data electric potential of the node, the data electric potential being obtained in a period t14 after a refresh operation of the memory circuit.

Abstract: Provided are a memory-type display device capable of improving image quality during a normal mode and a method for driving such a display device. Each memory circuit (MR1) includes: a node (PIX) (pixel electrode); a node (MRY) (memory electrode); a switch circuit (SW1); a first data-retention section (DS1) composed of a capacitor (Ca1); a data transfer section (TS1) composed of a transistor (N2); a second data-retention section (DS2) composed of a capacitor (Cb1); and a refresh output control section (RS1) including a transistor (N4). During the normal mode, and the capacitor (Ca1) and the capacitor (Cb1) are both used as auxiliary capacitors with the transistor (N2) in a conductive state and the transistor (N4) in a cutoff state.

Abstract: A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetting signal are active or inactive, as long as the initialization signal is active. The initialization signal becomes active before the end of the simultaneous selection, and then becomes inactive after the end of the simultaneous selection. This makes it possible to stabilize operation of the shift register after the end of simultaneous selection of a plurality of signal lines carried out by the display driving circuit at a predetermined timing.

Abstract: A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.

Abstract: Disclosed is a shift register for use in a display driving circuit that simultaneously selects signal lines, including, in a stage thereof: a flip-flop including an initialization terminal; and a signal generating circuit that receives a simultaneous selection signal and that generates an output signal of the stage by use of an output of the flip-flop, wherein: the output signal of the stage becomes active due to an activation of the simultaneous selection signal so as to be active during a period of the simultaneous selection; the output of the flip-flop is non-active while the initialization terminal, a set terminal, and a reset terminal of the flip-flop; and the initialization terminal of the flip-flop receives the simultaneous selection signal. This shift register makes it possible to downsize various drivers.

Abstract: A display driving circuit for driving a liquid crystal display panel includes a shift register including a plurality of shift register circuits provided in such a way as to correspond to a plurality of gate lines, respectively, the display driving circuit having latch circuits provided in such a way as to correspond one-by-one to the shift register circuits, a polarity signal being inputted to the latch circuits. When a internal signal generated by a shift register circuit becomes active, a latch circuit loads and retains the polarity signal, and an output from the latch circuit is supplied to a CS bus line. The internal signal becomes active before a first vertical scanning period of a display picture.

Abstract: A display driving circuit that carries out CC driving is configured such that retaining circuits are provided in such a way as to correspond one-by-one to their respective stages of a shift register, that a polarity signal CMI is inputted to each of the latch circuits, that when an internal signal Mn generated by a shift register at the nth stage becomes active, a latch circuit corresponding to the nth stage loads and retains the polarity signal CMI, that an output signal SRBOn from the shift register at the nth stage is supplied as a scanning signal to a gate line connected to pixels corresponding to the (n+1)th stage, and that an output from latch circuit corresponding to the nth stage is supplied as CSOUTn to a CS bus line forming capacitors with pixel electrodes of pixels corresponding to the nth stage.

Abstract: Provided is a shift register of a display-driving circuit which carries out simultaneous selection of a plurality of signal lines by using a simultaneous selection signal. A stage of the shift register includes (i) a set-reset type flip-flop and (ii) a signal generating circuit which generates an output signal of the stage by selectively outputting a signal in response to an output of the flip-flop. The output signal of the stage (i) becomes active due to an activation of the simultaneous selection signal and then (ii) remains active while the simultaneous selection is being performed, and the output from the flip-flop is inactive during a period in which a setting signal and a resetting signal are both being active. This makes it possible to quickly carry out the simultaneous selection of all the signal lines and the initialization of the shift register.

Abstract: Provided is an input apparatus capable of handling operation mistakes (erroneous operations) unintentionally performed by a user. An input apparatus 10 has a display unit 32 configured to display objects of folders arranged in a hierarchical structure, an input unit 34 configured to receive a pressing input to the display unit 32, a load detection unit 40 configured to detect a pressure load on the input unit 34, and a control unit 20, if the load detection unit 40 continuously detects a pressure load not satisfying a predetermined load standard for a predetermined period after satisfying the predetermined load standard while the display unit 32 is displaying objects of open folders, configured to control to close a lowest folder among the open folders.

Abstract: Provided is an input apparatus capable of handling operation mistakes (erroneous operations) unintentionally performed by a user. An input apparatus 10 has a display unit 32 configured to display objects of folders arranged in a hierarchical structure, an input unit 34 configured to receive a pressing input to the display unit 32, a load detection unit 40 configured to detect a pressure load on the input unit 34, and a control unit 20, if the load detection unit 40 continuously detects a pressure load satisfying a first load standard for a predetermined period while the display unit 32 is displaying an object of an open folder and the input unit 34 is receiving the pressing input at a position corresponding to an object of another folder different from the open folder, configured to control to open the another folder.

Abstract: An embodiment of the design support apparatus includes: a component database in which 3D shape data of each component in equipment and 3D layout data of each component are stored as component data for each component; a design criteria database in which information defining an inter-component distance between a first component and a second component to be verified and determination criteria used for verification of the inter-component distance are stored; a distance calculation unit which extracts component data of each of the first component and the second component from the component database, and calculates the inter-component distance from each of the extracted component data; and a determination unit which determines whether or not the calculated inter-component distance satisfies the determination criteria.

Abstract: A remover composition containing 1,3-propanediamine (a), 1-hydroxyethylidene-1, 1-diphosphonic acid (b) and water, wherein the remover composition contains the component (a) in an amount of from 0.2 to 30% by weight, the component (b) in an amount of from 0.05 to 10% by weight, and the water in an amount of from 60 to 99.75% by weight, and wherein the composition has a pH at 20° C. of from 9 to 13; and a remover composition containing an organic amine (A), an organic phosphonic acid (B), a linear sugar alcohol (C) and water, wherein the remover composition contains the component (A) in an amount of from 0.2 to 30% by weight, the component (B) in an amount of from 0.05 to 10% by weight, the component (C) in an amount of from 0.1 to 10% by weight, and the water in an amount of from 50 to 99.65% by weight, and wherein the composition has a pH at 20° C. of from 9 to 13.

Abstract: The present invention eliminates, for CC driving based on line inversion driving, the appearance of lateral stripes in a first frame in which an image corresponding to a video signal starts to be displayed. The present invention includes: a gate line driving circuit (30) which outputs a gate signal for turning on switching element on a corresponding row for a corresponding one of horizontal scanning periods which are sequentially allocated to the respective rows; a source bus line driving circuit which outputs a source signal for switching between line inversion driving and frame inversion driving; and a CS bus line driving circuit (40) which outputs a CS signal having a potential which is, after the horizontal scanning period for the row, switched in a direction (that is, either (from the low level to the high level or from the high level to the low level) determined in accordance with the polarity of the source signal during the horizontal scanning period.

Abstract: This invention relates to an agent, a composition and a product comprising at least one apoptosis-inducing substance, and at least one substance which inhibits expression and/or activity of an apoptosis-inhibiting substance; a method for inducing apoptosis or for treating a proliferative disease using one or more of them; a nucleic acid construct comprising a nucleic acid molecule encoding a protein to be expressed and a nucleic acid molecule which inhibits expression of an undesired protein; and a method for expressing a desired protein in a cell while inhibiting the expression of an undesired protein.

Abstract: A throttle control apparatus for an engine on a vehicle is provided, in which the number of component parts in the position detection means and the driven means is reduced to improve the accuracy in its position control and at the same time an integrated wiring is achieved and connectors are aggregated. The position detection means for detecting the position of a control valve, the driven means for controlling the position of the control valve, the means for processing control signals, an output from the position control means for controlling the position of the control valve are disposed within a sealed space defined by a body supporting a control valve shaft, and a cover. Based on the fact that the number of component parts of the position detection means may be reduced, the mechanical hysteresis and electrical hysteresis may also be reduced to improve the accuracy in controlling the control valve position, and it is possible to aggregate the connectors.