Patents by Inventor Yasushi Takahashi
Yasushi Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8455986Abstract: A semiconductor device featuring a semiconductor chip having a first main surface and a second, opposing main surface and including a MOSFET having source and gate electrodes formed on the first main surface and a drain electrode thereof formed on the second main surface, first and second conductive members acting as lead terminals for the source and gate electrodes, respectively, are disposed over the first main surface, each of the first and second conductive members has a part overlapped with the chip in a plan view, a sealing body sealing the chip and parts of the first and second conductive members such that a part of the first conductive member is projected outwardly from a first side surface of the sealing body and parts of the first and second conductive members are projected outwardly from the opposing second side surface of the sealing body in a plan view.Type: GrantFiled: April 30, 2012Date of Patent: June 4, 2013Assignees: Renesas Electronics Corporation, Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Publication number: 20130027903Abstract: Disclosed is a pointer-type meter with good uniformity of illumination of a display section even when there are few light sources, and with little or no displacement of each member when positioning is performed. A circuit board provided in the pointer-type meter comprises a first light-emitting element (332a) that emits light in a direction towards a first rotary shaft (3110). The pointer-type meter comprises: a first reflecting unit (321) positioned between the circuit board and a display plate (31) and that surrounds part of the circumference of the rotary shaft (3110) and reflects light towards the outer edge of a speed display unit (311); and a second reflecting unit (322) positioned between the circuit board and the display plate (31) and that reflects the light reflected by the first reflecting unit (321) to illuminate the speed display unit (311).Type: ApplicationFiled: April 15, 2011Publication date: January 31, 2013Applicant: NIPPON SEIKI CO., LTD.Inventor: Yasushi Takahashi
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Patent number: 8362614Abstract: A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.Type: GrantFiled: October 12, 2005Date of Patent: January 29, 2013Assignee: Elpida Memory, Inc.Inventors: Mitsuaki Katagiri, Hiroya Shimizu, Fumiyuki Osanai, Yasushi Takahashi, Seiji Narui
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Publication number: 20120320690Abstract: A semiconductor device that includes a semiconductor substrate. First and second mode registers are provided on the semiconductor substrate and store information, respectively. First and second circuits are provided on the semiconductor substrate. The first and second circuits have substantially the same configuration. The first and second circuits perform an operation in response to the information of the first and second mode registers, respectively.Type: ApplicationFiled: August 23, 2012Publication date: December 20, 2012Applicant: Elpida Memory, lnc.Inventors: Yasushi TAKAHASHI, Toru ISHIKAWA
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Publication number: 20120320686Abstract: A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the semiconductor substrate and electrically coupled to the first and second selection signal terminals of the controller, respectively. Multiple third data terminals are provided on the semiconductor substrate and electrically coupled to the first data terminals of the controller, respectively. Multiple fourth data terminals are provided on the semiconductor substrate and electrically coupled to the second data terminals of the controller, respectively. The first and third data terminals communicate first data in response to the first selection signal. The second and fourth data terminals communicate second data in response to the second selection signal.Type: ApplicationFiled: August 23, 2012Publication date: December 20, 2012Applicant: Elpida Memory, Inc.Inventors: Yasushi Takahashi, Toru Ishikawa
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Publication number: 20120266687Abstract: An engine gas sample device which can set a dilution rate of a sample gas without being restricted by warranty flow ranges of first and second flowmeters. The device makes it possible to dilute the sample gas at a low dilution rate, and is provided with a downstream-side dilution tunnel in which a part of exhaust gas flowing through an exhaust pipe is introduced as sample gas into a mixing part. A dilution gas flow path which is connected to an upstream side of the downstream-side dilution tunnel and includes the first flowmeter FM1, a diluted sample gas flow path which is connected to the downstream side of the downstream-side dilution tunnel and includes the second flowmeter FM2. A dilution gas discharge flow path which is connected to an upstream side of the mixing part in the downstream-side dilution tunnel and includes a third flowmeter FM3.Type: ApplicationFiled: November 22, 2010Publication date: October 25, 2012Applicant: HORIBA, LTD.Inventor: Yasushi Takahashi
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Patent number: 8274844Abstract: To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.Type: GrantFiled: May 20, 2010Date of Patent: September 25, 2012Assignee: Elpida Memory, Inc.Inventors: Yasushi Takahashi, Toru Ishikawa
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Publication number: 20120217556Abstract: A semiconductor device featuring a semiconductor chip having a first main surface and a second, opposing main surface and including a MOSFET having source and gate electrodes formed on the first main surface and a drain electrode thereof formed on the second main surface, first and second conductive members acting as lead terminals for the source and gate electrodes, respectively, are disposed over the first main surface, each of the first and second conductive members has a part overlapped with the chip in a plan view, a sealing body sealing the chip and parts of the first and second conductive members such that a part of the first conductive member is projected outwardly from a first side surface of the sealing body and parts of the first and second conductive members are projected outwardly from the opposing second side surface of the sealing body in a plan view.Type: ApplicationFiled: April 30, 2012Publication date: August 30, 2012Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 8244027Abstract: A vehicle environment recognition system includes stereo-image taking means for taking images of an environment around a subject vehicle and for outputting the images as a reference image and a comparative image, first stereo matching means for forming a first distance image on the basis of the reference image and the comparative image or on the basis of two images obtained by preprocessing the reference image and the comparative image, second stereo matching means for forming a second distance image on the basis of two images obtained by preprocessing the reference image and the comparative image in a different manner, detection means for detecting objects in the reference image on the basis of the first and second distance images, and selection means for selecting one of the results of detection based on the first and second distance images.Type: GrantFiled: January 23, 2009Date of Patent: August 14, 2012Assignee: Fuji Jukogyo Kabushiki KaishaInventor: Yasushi Takahashi
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Patent number: 8183607Abstract: A semiconductor device features a semiconductor chip including a MOSFET, a first electrode of the MOSFET disposed on an obverse surface of the chip, a second, control electrode of the MOSFET disposed on the obverse surface, a third electrode of the MOSFET disposed on a second, opposing surface of the chip, first, second, and third conductive members, each having top surface and opposing bottom surface, the first, second, and third conductive members connecting with the first, second, and third electrodes electrically, respectively, a sealing body having top and bottom surfaces and sealing parts of the first, second, and third conductive members, the first conductive member having first, second, and third contiguous portions, the first portion is positioned over the first electrode, the second is positioned between the first and second portions and the third portion is positioned under the obverse surface of the chip.Type: GrantFiled: July 25, 2011Date of Patent: May 22, 2012Assignees: Renesas Electronics Corporation, Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 8175334Abstract: A vehicle environment recognition apparatus includes stereo-image taking means for outputting a reference image of the surroundings of a subject vehicle, stereo matching means for correlating a parallax with each pixel block in the reference image by stereo matching, preceding-vehicle detecting means for detecting a preceding vehicle from the reference image on the basis of the parallax or the like, and smear determining means for searching a pixel column vertically extending in the reference image for brightnesses of pixels, the pixel column including a pixel block having a parallax less than or equal to a long-distance parallax threshold value corresponding to the long distance including infinity, and determining that a smear occurs when a ratio of the number of pixels having brightnesses more than or equal to a predetermined brightness to the total number of pixels in the pixel column is more than or equal to a predetermined ratio.Type: GrantFiled: March 24, 2009Date of Patent: May 8, 2012Assignee: Fuji Jukogyo Kabushiki KaishaInventor: Yasushi Takahashi
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Publication number: 20110298020Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: ApplicationFiled: July 25, 2011Publication date: December 8, 2011Inventors: Ryoichi KAJIWARA, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 8068379Abstract: A plurality of sub word lines each have a length equivalent to the division of a main word line along the extension direction thereof, arranged along a bit line crossing said main word line, and are connected with a plurality of memory cells. A first sub word select line arranged in parallel to the main word line is extended to a plurality of sub arrays arranged in the extension direction of the word line. A second sub word select line is connected to the corresponding one of said first sub word select line to be extended orthogonally to a word line driving circuit area of an adjacent sub array. In the sub word line driving circuit provided for each sub array, a sub word line is selected and deselected by signals supplied from said main word line and said second sub word select line.Type: GrantFiled: March 31, 1998Date of Patent: November 29, 2011Assignees: Hitachi, Ltd., Texas Instruments Inc.Inventors: Tsutomu Takahashi, Kouji Arai, Yasushi Takahashi, Atsuya Tanaka, Shunichi Sukegawa, Shinji Bessho, Masayuki Hira
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Patent number: 7985991Abstract: A semiconductor device features a semiconductor substrate with a MOSFET, an electrode for main current of the MOSFET disposed on a first major surface of the substrate, an electrode for control of the MOSFET disposed on the first major surface, a rear plane electrode of the MOSFET disposed on a second, opposing surface of the substrate, and an external connection terminal electrically connected to the rear plane electrode, the external electrode contains a first part, a second part and a third part, the first part is positioned over the rear plane electrode, the third part is positioned below the second major surface and the third part is connected via the second part to the first part.Type: GrantFiled: March 12, 2008Date of Patent: July 26, 2011Assignees: Renesas Electronics Corporation, Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 7904813Abstract: A regular edition video of a video title is split into shots or scenes with time codes, and provided information, which is the semantic evaluation of the story, is added to the respective scenes to organize the scene score. Necessary scenes for each purpose are extracted on the basis of the scene score and a threshold value (process Pr14). Video characteristic evaluation information is added for each shot constituting each of the extracted scenes so as to organize the shot score (process Pr16). Optimum shots for each of the extracted scenes are selected on the basis of a predetermined rule suitable for the purpose (process Pr16). The optimum shots are sequentially cut out from the regular edition video (process Pr21), thus automatically organizing a preview video suitable for the purpose (process Pr22).Type: GrantFiled: December 28, 1999Date of Patent: March 8, 2011Assignee: Sony CorporationInventors: Yasushi Takahashi, Kazuo Sugiyama, Makoto Watanabe
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Patent number: 7853122Abstract: The present invention is relative with a reproducing apparatus and a receiving apparatus for affording the impression or evaluation in line with the intention of a content supplier to the audience. The reproducing apparatus reproduces an optical disc (1) in which the contents and the estimated evaluation values are recorded at the outset. The estimated evaluation values recorded on the optical disc (1) have been set by the content supplier based on estimated impression or evaluation by the audience on the content. As the reproducing apparatus reproduces the content, the apparatus measures the reaction of the audience by a reaction value inputting unit (61), calculates the impression or evaluation by the audience for the content by a recognition evaluation value calculating unit (63) and compares the recognized evaluation values to the estimated evaluation values read out from the optical disc (1) in a control evaluation value calculating unit (53).Type: GrantFiled: February 6, 2002Date of Patent: December 14, 2010Assignee: Sony CorporationInventors: Masatoshi Miura, Yasushi Takahashi, Mikio Kamada, Yoshiaki Shibata, Hitoshi Kimura
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Publication number: 20100302874Abstract: To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.Type: ApplicationFiled: May 20, 2010Publication date: December 2, 2010Applicant: Elpida Memory, Inc.Inventors: Yasushi Takahashi, Toru Ishikawa
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Patent number: 7844941Abstract: When a space, sandwiched by large patterns having a predetermined size or more, is exposed using a charged particle beam, the space sandwiched by the large patterns is exposed using a common block mask having the space and edge portions of the large patterns on both sides of the space, and portions other than the edge portions of the large patterns on both sides are exposed by a variable rectangular beam or by using another block mask.Type: GrantFiled: July 24, 2009Date of Patent: November 30, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Yasushi Takahashi
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Patent number: 7812464Abstract: A semiconductor device and method having high output and having reduced external resistance is reduced and improved radiating performance. A MOSFET (70) has a connecting portion for electrically connecting a surface electrode of a semiconductor pellet and a plurality of inner leads, a resin encapsulant (29), a plurality of outer leads (37), (38) protruding in parallel from the same lateral surface of the resin encapsulant (29) and a header (28) bonded to a back surface of the semiconductor pellet and having a header protruding portion (28c) protruding from a lateral surface of the resin encapsulant (29) opposite to the lateral surface from which the outer leads protrude, wherein the header (28) has an exposed surface (28b) exposed from the resin encapsulant (29); the outer leads (37), (38) are bent; and the exposed of the outer leads (37), (38) are provided at substantially the same height.Type: GrantFiled: April 29, 2008Date of Patent: October 12, 2010Assignee: Renesas Electronics CorporationInventors: Toshinori Hirashima, Munehisa Kishimoto, Toshiyuki Hata, Yasushi Takahashi
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Patent number: D639399Type: GrantFiled: January 28, 2010Date of Patent: June 7, 2011Assignee: Toto Ltd.Inventors: Hiroyuki Takeuchi, Yasushi Takahashi, Masafumi Ishikawa