Patents by Inventor Yasushi Yamazaki

Yasushi Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6768522
    Abstract: In a TFT array substrate 10 of an electrooptical device, a scanning line 3a, a drain electrode 11, a first light shield layer 13, and a data line 3a are laminated over a channel region 1a′ of a TFT 30 and a second light shield layer 14 is laminated beneath the channel region 1a′. A side wall formation trench 16 is formed beside the channel region 1a′ of the TFT 30, and in the side wall formation trench a conductive layer having a light shield property is concurrently formed with the first light shield layer 13 thereby a light shield side wall 131 is formed. By three-dimensionally blocking light's entry towards the channel region 1a′, obliquely or laterally incident light is prevented from entering the channel region of a pixel switching TFT, and the TFT 30 is free from erratic operations and reliability degradation.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: July 27, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Masahiro Yasukawa, Yasushi Yamazaki
  • Patent number: 6704415
    Abstract: An echo canceler makes it possible to adaptably control a power of speech reception voice and to reduce distortion of a voice output from a speaker. The echo canceler has a basic structure includes a power control section controlling a power for a speech reception voice, a first filtering section removing a particular component from an output of the power control section, an echo canceling section removing echo components of a speech reception voice, which are added to a speech transmission voice, a second filtering section filtering particular components of the speech reception and transmission voices, and a state judgement section judging existences of the speech reception and transmission voices from an output of the second filtering section and controlling a power attenuation amount of the power control section based on the judgement result.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: March 9, 2004
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Katayama, Yasushi Yamazaki, Hitoshi Matsuzawa, Yoshihiro Tomita, Mutsumi Saito, Hisanari Kimura
  • Publication number: 20040015457
    Abstract: The collating device includes the Formant estimation section that estimates feature amount data that represents a time-based change in frequencies of first and second Formants from voice data input through the microphone. The difference computing section calculates a difference between some reference feature amount data and the feature amount data as the feature-amount difference data. This feature-amount difference data is stored in a database. The feature-amount difference data corresponding to voice data input upon collation is collated with the feature-amount difference data registered in the database, and the result is output.
    Type: Application
    Filed: October 24, 2001
    Publication date: January 22, 2004
    Applicant: Fujitsu Limited
    Inventors: Takeshi Otani, Yasushi Yamazaki, Hitoshi Sasaki
  • Patent number: 6667517
    Abstract: An electrooptical device including a semiconductor device which is formed in a semiconductor layer on an insulating layer in such a manner that floating substrate effects which are essential in a SOI structure is suppressed without reducing the aperture ratio. The thickness of a semiconductor layer in pixel areas is limited to a range equal to or less than 100 nm, p-channel transistors having less floating substrate effects are employed as pixel transistors, and recombination centers are produced by means of implantation of Ar ions, thereby avoiding accumulation of excess carriers, thereby realizing an electrooptical device in which floating substrate effects are suppressed without forming a body contact and which has a high aperture ratio and a low optically induced leakage current.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: December 23, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Yasushi Yamazaki
  • Publication number: 20030210363
    Abstract: In a TFT array substrate 10 of an electrooptical device, a scanning line 3a, a drain electrode 11, a first light shield layer 13, and a data line 3a are laminated over a channel region 1a′ of a TFT 30 and a second light shield layer 14 is laminated beneath the channel region 1a′. A side wall formation trench 16 is formed beside the channel region 1a′ of the TFT 30, and in the side wall formation trench a conductive layer having a light shield property is concurrently formed with the first light shield layer 13 thereby a light shield side wall 131 is formed. By three-dimensionally blocking light's entry towards the channel region 1a′, obliquely or laterally incident light is prevented from entering the channel region of a pixel switching TFT, and the TFT 30 is free from erratic operations and reliability degradation.
    Type: Application
    Filed: May 5, 2003
    Publication date: November 13, 2003
    Applicant: Seiko Epson Corporation
    Inventors: Masahiro Yasukawa, Yasushi Yamazaki
  • Publication number: 20030206265
    Abstract: In a TFT array substrate 10 of an electrooptical device, a scanning line 3a, a drain electrode 11, a first light shield layer 13, and a data line 3a are laminated over a channel region 1a′ of a TFT 30 and a second light shield layer 14 is laminated beneath the channel region 1a′. A side wall formation trench 16 is formed beside the channel region 1a′ of the TFT 30, and in the side wall formation trench a conductive layer having a light shield property is concurrently formed with the first light shield layer 13 thereby a light shield side wall 131 is formed. By three-dimensionally blocking light's entry towards the channel region 1a′, obliquely or laterally incident light is prevented from entering the channel region of a pixel switching TFT, and the TFT 30 is free from erratic operations and reliability degradation.
    Type: Application
    Filed: May 5, 2003
    Publication date: November 6, 2003
    Applicant: Seiko Epson Corporation
    Inventors: Masahiro Yasukawa, Yasushi Yamazaki
  • Publication number: 20030187640
    Abstract: A speech input device is provided with a microphone which inputs speech, a key entry detector which detects an operation of a key section which serves as a man-machine interface, and a noise eliminator which eliminates a component of an operation sound from the speech that is input into the microphone within a period in which the key entry detector detects the operation.
    Type: Application
    Filed: November 13, 2002
    Publication date: October 2, 2003
    Applicant: Fujitsu, Limited
    Inventors: Takeshi Otani, Yasushi Yamazaki
  • Patent number: 6628367
    Abstract: The invention provides an electrooptical device, such as a liquid-crystal device that presents a high-contrast, bright and high-quality image, by reducing a malfunction due to a transverse electric field in an electrooptical material, such as a liquid crystal. The electrooptical device includes pixel electrodes on a TFT array substrate and a counter electrode on a counter substrate. Arranged beneath the pixel electrodes in the TFT array substrate are protrusions in an area facing a spacing between adjacent pixel electrodes. The method for manufacturing such an electrooptical device includes: forming a pattern including a wiring, a TFT, etc. on the TFT array substrate; planarizing the surface of a laminate of the substrate including the pattern; and forming the protrusion by subjecting the planarized surface to photolithographic and etching processes.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: September 30, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Yukiya Hirabayashi, Yasushi Yamazaki
  • Publication number: 20030179324
    Abstract: The invention provides a liquid crystal display device which makes it possible to increase functionality by mounting a function element without having to externally mount the function element onto an area near and outside of a liquid crystal display panel. A liquid crystal display device includes a plurality of pixels disposed in a matrix form and a drive element to drive the pixels. A function element, having a function that is different from the function of the drive element, is disposed in an area including the plurality of pixels and used to display. By this, it is possible to increase functionality because function elements having various functions can be incorporated inside a panel.
    Type: Application
    Filed: December 27, 2002
    Publication date: September 25, 2003
    Applicant: Seiko Epson Corporation
    Inventor: Yasushi Yamazaki
  • Publication number: 20030116801
    Abstract: A structure is provided which suppresses a parasitic bipolar effect without decreasing the breakdown voltage at the junctions between the excessive carrier extracting region and source/drain regions of a MOS transistor for a voltage of approximately 15 volts in a semiconductor device formed on a semiconductor layer on an insulating layer. In the MOS transistor having a source tied body structure, a semiconductor regions having a low impurity concentration is formed between a regions for extracting excessive carriers and source/drain regions. Thus, the breakdown voltage at the junctions between the extracting regions and the source/drain regions is increased and a parasitic bipolar effect is suppressed without breakdown between the extracting regions and the source/drain regions.
    Type: Application
    Filed: December 4, 2002
    Publication date: June 26, 2003
    Applicant: Seiko Epson Corporation
    Inventor: Yasushi Yamazaki
  • Publication number: 20030116802
    Abstract: A method of manufacturing a semiconductor substrate includes the processes of: forming an insulation film on a surface of a semiconductor substrate main body; forming an ion shield member having a predetermined shape on the insulation film; implanting an ion into the semiconductor substrate main body from a side on which the insulation film is formed, to thereby form an ion implantation layer; removing the ion shield member; laminating the insulation film and a support substrate onto each other; and separating the semiconductor substrate main body from the support substrate at a portion of the ion implantation layer.
    Type: Application
    Filed: December 2, 2002
    Publication date: June 26, 2003
    Applicant: Seiko Epson Corporation
    Inventors: Yasushi Yamazaki, Yukiya Hirabayashi
  • Patent number: 6583830
    Abstract: The present invention provides an electrooptical device wherein in a thin-film transistor (TFT) array substrate of the electrooptical device, a scanning line, a drain electrode, a first light shield layer, and a data line are laminated over a channel region of a TFT and a second light shield layer is laminated beneath the channel region. A side wall formation trench is formed beside the channel region of the TFT, and in the side wall formation trench a conductive layer having a light shield property is concurrently formed with the first light shield layer thereby a light shield side wall is formed. By three-dimensionally blocking the entry of light towards the channel region, obliquely or laterally incident light is prevented from entering the channel region of a pixel switching TFT, and the TFT is free from erratic operations and reliability degradation.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: June 24, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Masahiro Yasukawa, Yasushi Yamazaki
  • Patent number: 6573533
    Abstract: A structure is provided which suppresses a parasitic bipolar effect without decreasing the breakdown voltage at the junctions between the excessive carrier extracting region and source/drain regions of a MOS transistor for a voltage of approximately 15 volts in a semiconductor device formed on a semiconductor layer on an insulating layer. In the MOS transistor having a source tied body structure, a semiconductor regions having a low impurity concentration is formed between a regions for extracting excessive carriers and source/drain regions. Thus, the breakdown voltage at the junctions between the extracting regions and the source/drain regions is increased and a parasitic bipolar effect is suppressed without breakdown between the extracting regions and the source/drain regions.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: June 3, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Yasushi Yamazaki
  • Patent number: 6573575
    Abstract: In a semiconductor device including a plurality of n-channel transistors having different threshold voltages and each having a gate electrode including an n-type polysilicon film, the impurity concentration of the n-type polysilicon film included in the gate electrode of an n-channel transistor having a relatively high threshold, is lower than the impurity concentration of the n-type polysilicon film included in the gate electrode of an n-channel transistor having a relatively low threshold. Thus, the n-channel transistor having a relatively high threshold can be realized in the semiconductor device, without various problems such as an increased leak current caused by increasing the impurity concentration of the channel region, the lowered subthreshold factor caused by using the p+ polysilicon film in the gate electrode, the deteriorated insulating performance of the gate oxide film, the increased number of fabricating steps, or the dropped reliability of the transistor.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: June 3, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Yasushi Yamazaki
  • Publication number: 20030057489
    Abstract: The invention provides a method for manufacturing a semiconductor substrate having the SOI structure composed of a supporting substrate and an SOI layer, which have thermal expansion coefficients different from each other, can be formed. In addition, a semiconductor substrate, and an electrooptic device and an electronic apparatus are also provided. When a substrate having the SOI structure is formed, a groove is formed in a single crystal silicon layer, so that island-shaped single crystal silicon layers are formed. Subsequently, heat treatment is performed. Consequently, since thermal stress caused by the difference in thermal expansion coefficient between a supporting substrate and the single crystal silicon layer is reduced by the groove, even when heat treatment for improving a bonding strength or an oxidation step is performed, a high-quality single crystal silicon layer having no dislocation and cracks therein can be obtained.
    Type: Application
    Filed: August 22, 2002
    Publication date: March 27, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yasushi Yamazaki
  • Patent number: 6522753
    Abstract: In an active noise control method of the present invention, a noise detection signal from a noise referring microphone which detects ambient noise is inputted into noise processing units of different types to produce noise silencing signals. A selected noise silencing signal is inputted into a receiver or a speaker together with a reception signal via an adder, so that a regenerated tone from the noise silencing signal silences the ambient noise, When a nonconformance detecting unit judges that the selected noise silencing signal exceeds a predetermined range, the corresponding noise processing unit is judged to be incompatible, and a switch control unit controls a switch to select another one of the noise processing units.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: February 18, 2003
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Matsuzawa, Yasushi Yamazaki
  • Publication number: 20030011740
    Abstract: A liquid crystal device has inorganic alignment layers (36, 42) disposed on a surface of a liquid crystal layer side of a pair of the substrates, when the range of the average pre-tilt angle &thgr; of liquid crystal molecules 50a of the liquid crystal layer is 5 degrees≦&thgr;≦20 degrees, twist angle &phgr; of the liquid crystal molecules (50a) of the liquid crystal layer, cell gap d, and helical pitch P of the liquid crystal molecules of the liquid crystal layer satisfy the relationship of (0.6/360)&phgr;<d/P<(1.4/360)&phgr;, and when the range of the average pre-tilt angle &thgr; of liquid crystal molecules 50a of the liquid crystal layer is &thgr;>20 degrees, twist angle &phgr; of the liquid crystal molecules (50a) of the liquid crystal layer, cell gap d, and helical pitch P of the liquid crystal molecules of the liquid crystal layer satisfy the relationship of (0.8/360)&phgr;<d/P<(1.6/360)&phgr;.
    Type: Application
    Filed: February 19, 2002
    Publication date: January 16, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takaaki Tanaka, Yasushi Yamazaki
  • Publication number: 20020150265
    Abstract: In an apparatus which estimates characteristics of a surrounding noise only when an input signal is soundless and performs a noise reduction or suppression of the input signal based on the estimated result, a signal noise ratio is estimated from the input signal, and an automatic switch or an automatic adjustment is performed so as to execute a noise reduction only when the signal noise ratio is good, otherwise to avoid the noise reduction or make the noise reduction degree smaller.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 17, 2002
    Inventors: Hitoshi Matsuzawa, Yasushi Yamazaki
  • Publication number: 20020113929
    Abstract: An active-matrix liquid crystal display is composed of an active matrix substrate, a liquid crystal, and an opposite substrate having a common electrode. The active matrix substrate fabricates a first group of pixel electrodes that are aligned and supplied with picture signals of a first polarit, and a second group of pixel electrodes that are aligned to adjoin with the first group of pixel electrodes respectively and are supplied witb picture signals of a second polari. An inorganic orientation film is formed on the surfac of the active matrix substrate to provide a first orientation direction (Ra) to its proximal liquid crystal moleclges, while an organic orientation film is formed on the surface ofthe opposite substrate to provide a second orientation direction sb), rectangularly crossing the first oneenation direction, to its proximal liquid-crstal molecules.
    Type: Application
    Filed: February 14, 2002
    Publication date: August 22, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Yasushi Yamazaki, Takaaki Tanaka
  • Publication number: 20020057403
    Abstract: In a TFT array substrate 10 of an electrooptical device, a scanning line 3a, a drain electrode 11, a first light shield layer 13, and a data line 3a are laminated over a channel region 1a′ of a TFT 30 and a second light shield layer 14 is laminated beneath the channel region 1a′. A side wall formation trench 16 is formed beside the channel region 1a′ of the TFT 30, and in the side wall formation trench a conductive layer having a light shield property is concurrently formed with the first light shield layer 13 thereby a light shield side wall 131 is formed. By three-dimensionally blocking light's entry towards the channel region 1a′, obliquely or laterally incident light is prevented from entering the channel region of a pixel switching TFT, and the TFT 30 is free from erratic operations and reliability degradation.
    Type: Application
    Filed: November 6, 2001
    Publication date: May 16, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Masahiro Yasukawa, Yasushi Yamazaki