Patents by Inventor Yasushi Yamazaki
Yasushi Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020021402Abstract: The invention provides an electrooptical device, such as a liquid-crystal device that presents a high-contrast, bright and high-quality image, by reducing a malfunction due to a transverse electric field in an electrooptical material, such as a liquid crystal. The electrooptical device includes pixel electrodes on a TFT array substrate and a counter electrode on a counter substrate. Arranged beneath the pixel electrodes in the TFT array substrate are protrusions in an area facing a spacing between adjacent pixel electrodes. The method for manufacturing such an electrooptical device includes: forming a pattern including a wiring, a TFT, etc. on the TFT array substrate; planarizing the surface of a laminate of the substrate including the pattern; and forming the protrusion by subjecting the planarized surface to photolithographic and etching processes.Type: ApplicationFiled: June 11, 2001Publication date: February 21, 2002Applicant: Seiko Epson CorporationInventors: Yukiya Hirabayashi, Yasushi Yamazaki
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Patent number: 6343130Abstract: A stereophonic sound processing system for localizing a sound image at desired locations using devices including a headphone and a speaker, includes a processing unit for generating stereophonic sound on the basis of an input signal. The processing unit includes: a plurality of stereophonic filter units each including an FIR filter for processing an input signal; a selecting unit for selecting one of the plurality of stereophonic filter units in accordance with a desired factor; wherein the processing unit controls the selected stereophonic filter unit so as to generate stereophonic sound on the basis of a processed result supplied by the selected stereophonic filter unit.Type: GrantFiled: February 25, 1998Date of Patent: January 29, 2002Assignee: Fujitsu LimitedInventor: Yasushi Yamazaki
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Publication number: 20020001938Abstract: When contact holes are concurrently formed in an inter-level insulating layer over an impurity region in a silicon substrate and a polycide line on a thick field oxide layer, the manufacturer interrupts the etching at the refractory metal silicide layer of the polycide line, and restarts the etching after removal of a part of the refractory metal silicide layer exposed to the short contact hole, thereby preventing the impurity region from undesirable etching for the refractory metal silicide layer.Type: ApplicationFiled: February 11, 1999Publication date: January 3, 2002Inventor: YASUSHI YAMAZAKI
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Patent number: 6335242Abstract: In a method for fabricating a semiconductor device including a stacked structure memory cell having a transistor and a capacitor stacked over the transistor, a lower electrode of opposing electrodes of the capacitor is formed by forming a high-concentration impurity-doped amorphous silicon layer on an interlayer insulator film and patterning the amorphous silicon layer into an electrode shape, generating crystal nuclei on a surface of the patterned amorphous silicon layer and growing the crystal nuclei to form crystalline grains of silicon on an upper surface and a side surface of the patterned amorphous silicon layer, and forming a high-concentration impurity-doped polysilicon film on the crystalline grains and the amorphous silicon layer. Thus, the impurity concentration at the surface of the crystalline grains is compensated for. As a result, a stacked capacitor having less bias voltage dependency of the capacitance can be obtained.Type: GrantFiled: May 20, 1999Date of Patent: January 1, 2002Assignee: NEC CorporationInventor: Yasushi Yamazaki
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Publication number: 20010012368Abstract: A stereophonic sound processing system for localizing a sound image at desired locations using devices including a headphone and a speaker, includes a processing unit for generating stereophonic sound on the basis of an input signal. The processing unit includes: a plurality of stereophonic filter units each including an FIR filter for processing an input signal; a selecting unit for selecting one of the plurality of stereophonic filter units in accordance with a desired factor; wherein the processing unit controls the selected stereophonic filter unit so as to generate stereophonic sound on the basis of a processed result supplied by the selected stereophonic filter unit.Type: ApplicationFiled: February 25, 1998Publication date: August 9, 2001Inventor: YASUSHI YAMAZAKI
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Patent number: 6259793Abstract: An apparatus for continuously reproducing plural sound data has a start end/terminal end determination unit for determining the start end/terminal end of the continued respective sound data, a fade-in/fade-out unit for carrying out fade-in process at the start end of plural respective sound data and/or fade-out process at the terminal end of the same, a data output unit for continuously outputting the plural sound data which have been subjected to fade-in process and/or fade-out process, and a reproduction unit for reproducing the outputted plural sound data. In reproducing continuously the plural sound data, no noise is generated at the joint portion of the adjacent sound data.Type: GrantFiled: February 25, 1998Date of Patent: July 10, 2001Assignee: Fujitsu LimitedInventors: Nobuyuki Washio, Yasushi Yamazaki
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Patent number: 5909662Abstract: The present invention relates to a speech processing device equipped with both a speech coding/decoding function and a speech recognition function, and is aimed at providing a speech processing device equipped with both a speech coding/decoding function and a speech recognition function by using a small amount of memory.Type: GrantFiled: March 11, 1997Date of Patent: June 1, 1999Assignee: Fujitsu LimitedInventors: Yasushi Yamazaki, Tomohiko Taniguchi, Tomonori Sato, Hitoshi Matsuzawa, Chiharu Kawai
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Patent number: 5895963Abstract: A semiconductor device according to the present invention comprises a fuse provided on a substrate, a first insulating layer formed on the substrate and the first insulating layer, a first wiring formed on the first insulating layer, a second insulating layer formed on the first wiring, the second insulating layer including a plurality of insulating films including a water absorptive overcoat, a second wiring formed on the second insulating layer, an opening portion formed in a portion of the second insulating layer corresponding to the fuse by selectively removing the portion and having a side face formed by an exposed portion of the second insulating layer and a bottom face formed by the exposed first insulating layer, a side wall film formed of the same material as that of the second wiring and covering the exposed side face of the opening portion and a passivation film formed on the second insulating layer, the second insulating layer and the side wall film.Type: GrantFiled: February 6, 1998Date of Patent: April 20, 1999Assignee: NEC CorporationInventor: Yasushi Yamazaki
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Patent number: 5888862Abstract: A contact hole and an opening(accessory mark) is formed in a insulation film. Then, a first polysilicon film is grown by reduced pressure CVD process. After a silicon oxide film which is to form a core of the cylindrical stack is grown by about 1300 nm by a normal pressure CVD process, the core silicon oxide film and the first polysilicon film is patterned. Next, using Chemical Mechanical Polishing process, the whole wafer surface is polished by about 900 nm to form a core oxide film having fully flat surface in a height of about 400 nm from the non-open part of contact. By this process, production of harmful particles at the time of removal of the core oxide film can be prevented. Accordingly, the product yield can be improved.Type: GrantFiled: June 5, 1998Date of Patent: March 30, 1999Assignee: NEC CorporationInventor: Yasushi Yamazaki
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Patent number: 5847444Abstract: A semiconductor device has a memory cell area which contains a component having a height and a peripheral circuit area free of a component having a height. The first area includes a interlayer insulating film comprising a first interlayer film as an uppermost insulating film. The second area includes an interlayer insulating film comprising the first interlayer film and a second interlayer film disposed directly on the first interlayer film and having a chemical mechanical polishing rate greater than the first interlayer film. The interlayer insulating film in the memory cell area has a surface higher than the interlayer insulating film in the peripheral circuit area.Type: GrantFiled: August 30, 1996Date of Patent: December 8, 1998Assignee: NEC CorporationInventor: Yasushi Yamazaki
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Patent number: 5717724Abstract: To improve the voice quality of a digital mobile communication system such as a car telephone or portable telephone when outdoor background noises are superimposed on voices. To achieve the above object, a voice decoding apparatus comprises noise superimposed part detecting means for discriminating between a noise part containing only noises and a voice part containing voices from signal encoded at a transmission side, voice decoding means for decoding an encoded signal in the voice part into a waveform signal, noise decoding means for decoding an encoded signal in the noise part into a waveform signal, and noise control means for controlling the frequency characteristic of said noise part by controlling said noise decoding means when said noise superimposed part detecting means judges the noise part.Type: GrantFiled: August 4, 1995Date of Patent: February 10, 1998Assignee: Fujitsu LimitedInventors: Yasushi Yamazaki, Tomohiko Taniguchi, Tomonori Sato, Hisanari Kimura
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Patent number: 5655134Abstract: A link information storer stores link connection information and a node information storer stores node label information by sequentially searching links from the beginning of a network when data in a network structure are configured by linking nodes according to the relations among nodes (N), which represent basic units of data. The link information storer stores a previous or next node identifier of each link. When a plurality of links share the same next node, their pieces of link information are stored successively. To indicate that the next nodes are the same, a positive or negative sign is attached to the node numbers showing the previous nodes. Link numbers are uniquely assigned to respective links.Type: GrantFiled: July 13, 1994Date of Patent: August 5, 1997Assignee: Fujitsu LimitedInventor: Yasushi Yamazaki
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Patent number: 5607869Abstract: In a method for manufacturing an asymmetrical LDD type MOS transistor, low concentration impurity diffusion regions are formed within a semiconductor substrate on both sides of a gate electrode. Then, sidewall insulating layers are formed on both sides of the gate electrode, and, after that, high concentration inpurity diffusion regions are formed within the semiconductor substrate on both sides of the sidewall insulating layers. Then, one of the sidewall insulating layers is removed simulataneously with formation of contact holes in an interlayer formed on on the entire surface. Finally, impurities are implanted with a mask of the interlayer, to enlarge one of the high concentration impurity diffusion regions.Type: GrantFiled: February 1, 1996Date of Patent: March 4, 1997Assignee: NEC CorporationInventor: Yasushi Yamazaki
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Patent number: 5577162Abstract: A dynamic programming or DP matching system for speech recognition. Upon DP matching, cumulative distance is compared with a threshold value at every sampling time point of a speech pattern to thereby restrict the number of DP paths in succeeding matching processes. The number of DP paths remaining at each speech pattern sampling time point is monitored by a monitoring module for altering a threshold value so as to decrease the number of the DP paths. When DP path number becomes excessively large, the threshold is increased to thereby decrease the DP path number. Capacity of a DP data storing memory can be reduced while preventing the matching capability from being lowered.Type: GrantFiled: October 11, 1994Date of Patent: November 19, 1996Assignee: Fujitsu LimitedInventor: Yasushi Yamazaki
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Patent number: 5547888Abstract: In a method for manufacturing an asymmetrical LDD type MOS transistor, low concentration impurity diffusion regions are formed within a semiconductor substrate on both sides of a gate electrode. Then, sidewall insulating layers are formed on both sides of the gate electrode, and, after that, high concentration inpurity diffusion regions are formed within the semiconductor substrate on both sides of the sidewall insulating layers. Then, one of the sidewall insulating layers is removed simulataneously with formation of contact holes in an interlayer formed on on the entire surface. Finally, impurities are implanted with a mask of the interlayer, to enlarge one of the high concentration impurity diffusion regions.Type: GrantFiled: December 22, 1994Date of Patent: August 20, 1996Assignee: NEC CorporationInventor: Yasushi Yamazaki
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Patent number: 5474948Abstract: A polysilicon resistor element and a semiconductor device using the same are disclosed. The polysilicon resistor element has a resistive polysilicon film formed on a predetermined interlayer insulating film of a semiconductor chip. The resistive polysilicon film is covered by an insulating film having holes and high melting point metal films are formed in self-alignment to the holes. The high melting metal film constitutes one of lead portions of the polysilicon resistor element. A diffusion of the high melting point metal film due to heat treatment during fabrication, which causes an effective length of the resistor element, becomes negligible and reproducibility is improved.Type: GrantFiled: December 18, 1992Date of Patent: December 12, 1995Assignee: NEC CorporationInventor: Yasushi Yamazaki
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Patent number: 5460995Abstract: A grounding wiring layer is provided on the substantially entire region between driver MOS transistors and load MOS thin film transistors of a flip-flop type memory cell. The contact holes for connecting the gate electrodes of the MOS thin film transistors with storage nodes are formed by providing a side wall on the inner wall of each of the contact hole portions formed in the grounding wiring layer and inter-layer insulating films sandwiching it. Thus, the impedance of the grounding wiring layer can be reduced to stabilize the operation of a miniaturized SRAM memory cell using the load MOS thin film transistors. The resistance against for software error caused by .alpha.-ray can also be improved.Type: GrantFiled: June 15, 1994Date of Patent: October 24, 1995Assignee: NEC CorporationInventors: Junji Kiyono, Yasushi Yamazaki
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Patent number: 5352916Abstract: A grounding wiring layer is provided on the substantially entire region between driver MOS transistors and load MOS thin film transistors of a flip-flop type memory cell. The contact holes for connecting the gate electrodes of the MOS thin film transistors with storage nodes are formed by providing a side wall on the inner wall of each of the contact hole portions formed in the grounding wiring layer and inter-layer insulating films sandwiching it. Thus, the impedance of the grounding wiring layer can be reduced to stabilize the operation of a miniaturized SRAM memory cell using the load MOS thin film transistors. The resistance against soft error caused by .alpha.-ray can also be improved.Type: GrantFiled: August 28, 1992Date of Patent: October 4, 1994Assignee: NEC CorporationInventors: Junji Kiyono, Yasushi Yamazaki
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Patent number: 5091768Abstract: A semiconductor device has a funnel shaped contact window for providing an inter-level connection between a lower silicon or polysilicon film and an upper metal wiring strip, and the funnel shaped contact window is formed in an inter-level insulating film structure consisting of a lower insulating film of phosphosilicate glass and an upper insulating film of silicon dioxide, since an isotropical etching is firstly applied to the silicon dioxide film and followed by an anisotropical etching to the phosphosilicate glass film by using the same mask layer, the lower portion of the contact window is smaller in cross sectional area than the upper portion, and the funnel shaped contact window thus formed is effective to create a smooth topography of an upper metal wiring strip for preventing from undesirable disconnection.Type: GrantFiled: January 18, 1990Date of Patent: February 25, 1992Assignee: NEC CorporationInventor: Yasushi Yamazaki