Patents by Inventor Yasutoshi Okuno

Yasutoshi Okuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20190035691
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 31, 2019
    Inventors: YASUTOSHI OKUNO, CHENG-YI PENG, ZIWEI FANG, I-MING CHANG, AKIRA MINEJI, YU-MING LIN, MENG-HSUAN HSIAO
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190006371
    Abstract: A semiconductor device includes a substrate having a semiconductor fin, in which the semiconductor fin has a first sidewall and a second sidewall opposite to the first sidewall; an epitaxy structure in contact with the first sidewall of the semiconductor fin; and a spacer in contact with the second sidewall of the semiconductor fin and the epitaxy structure.
    Type: Application
    Filed: February 27, 2018
    Publication date: January 3, 2019
    Inventors: Tetsu OHTOU, Ching-Wei TSAI, Kuan-Lun CHENG, Yasutoshi OKUNO, Jiun-Jia HUANG
  • Multi-layer semiconductor device structure
    Patent number: 10157914
    Abstract: One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yasutoshi Okuno, Yi-Tang Lin
  • SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURE WITH TWO CHANNEL LAYERS AND MANUFACTURING METHOD THEREOF
    Publication number: 20180254347
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.
    Type: Application
    Filed: May 7, 2018
    Publication date: September 6, 2018
    Inventors: Tung Ying LEE, Chien-Chang SU, Wang-Chun HUANG, Yasutoshi OKUNO
  • METHOD OF PROVIDING LAYOUT DESIGN OF SRAM CELL
    Publication number: 20180166433
    Abstract: A method of providing a layout design of an SRAM cell includes: providing a substrate layout comprising a first oxide diffusion area, a second oxide diffusion area, a first polysilicon layout, and a second polysilicon layout, wherein the first polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area, and the second polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area; forming a first pull-up transistor on the first oxide diffusion area and the first polysilicon layout; forming a first pull-down transistor on the second oxide diffusion area and the first polysilicon layout; forming a second pull-up transistor on the first oxide diffusion area and the second polysilicon layout; and forming a second pull-down transistor on the second oxide diffusion area and second first polysilicon layout.
    Type: Application
    Filed: October 5, 2017
    Publication date: June 14, 2018
    Inventors: HIDEHIRO FUJIWARA, TETSU OHTOU, CHIH-YU LIN, HSIEN-YU PAN, YASUTOSHI OKUNO, YEN-HUEI CHEN
  • REPLACEMENT CONTACTS
    Publication number: 20180166379
    Abstract: The present disclosure describes a method of forming a replacement contact. For example, the replacement contact can include a metal with one or more first sidewall surfaces and a top surface. A first dielectric can be formed to abut the one or more first sidewall surfaces of the metal. A second dielectric can be formed over the first dielectric and the top surface of the metal. An opening in the second dielectric can be formed. A metal oxide structure can be selectively grown on the top surface of the metal, where the metal oxide structure has one or more second sidewall surfaces. One or more spacers can be formed to abut the one or more second sidewall surfaces of the metal oxide structure. Further, the metal oxide structure can be removed.
    Type: Application
    Filed: March 16, 2017
    Publication date: June 14, 2018
    Inventors: Yee-Chia YEO, Teng-Chun Tsai, Yasutoshi Okuno
  • Method for forming semiconductor structure with epitaxial growth structure
    Patent number: 9997615
    Abstract: Methods for forming semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a hard mask structure over a substrate and etching the substrate through an opening of the hard mask structure to form a trench. The method for manufacturing a semiconductor structure further includes removing a portion of the hard mask structure to enlarge the opening and forming an epitaxial-growth structure in the trench and the opening.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Yu Yeh, Chung-Cheng Wu, Cheng-Long Chen, Gwan-Sin Chang, Pang-Yen Tsai, Yen-Ming Chen, Yasutoshi Okuno, Ying-Hsuan Wang
  • MULTI-LAYER SEMICONDUCTOR DEVICE STRUCTURE
    Publication number: 20180130797
    Abstract: One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening.
    Type: Application
    Filed: January 10, 2018
    Publication date: May 10, 2018
    Inventors: Yasutoshi OKUNO, Yi-Tang LIN
  • Semiconductor device including fin structure with two channel layers and manufacturing method thereof
    Patent number: 9966469
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: May 8, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Chien-Chang Su, Wang-Chun Huang, Yasutoshi Okuno
  • Multi-layer semiconductor device structure
    Patent number: 9893056
    Abstract: One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yasutoshi Okuno, Yi-Tang Lin
  • SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURE WITH TWO CHANNEL LAYERS AND MANUFACTURING METHOD THEREOF
    Publication number: 20170162696
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Inventors: Tung Ying LEE, Chien-Chang SU, Wang-Chun HUANG, Yasutoshi OKUNO
  • METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH EPITAXIAL GROWTH STRUCTURE
    Publication number: 20170154978
    Abstract: Methods for forming semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a hard mask structure over a substrate and etching the substrate through an opening of the hard mask structure to form a trench. The method for manufacturing a semiconductor structure further includes removing a portion of the hard mask structure to enlarge the opening and forming an epitaxial-growth structure in the trench and the opening.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Yu YEH, Chung-Cheng WU, Cheng-Long CHEN, Gwan-Sin CHANG, Pang-Yen TSAI, Yen-Ming CHEN, Yasutoshi OKUNO, Ying-Hsuan WANG
  • Semiconductor structure with enhanced contact and method of manufacture the same
    Patent number: 9647115
    Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 9, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yasutoshi Okuno, Cheng-Long Chen, Meng-Chun Chang, Sung-Li Wang, Yi-Fang Pai, Yusuke Oniki
  • SEMICONDUCTOR STRUCTURE WITH ENHANCED CONTACT AND METHOD OF MANUFACTURE THE SAME
    Publication number: 20170110578
    Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well.
    Type: Application
    Filed: October 14, 2015
    Publication date: April 20, 2017
    Inventors: Yasutoshi OKUNO, Cheng-Long CHEN, Meng-Chun CHANG, Sung-Li WANG, Yi-Fang PAI, Yusuke ONIKI
  • Methods for probing semiconductor fins through four-point probe and determining carrier concentrations
    Patent number: 9627280
    Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Yasutoshi Okuno, Ling-Yen Yeh, Chi-Yuan Shih, Yuan-Fu Shao, Wei-Chun Tsai
  • Semiconductor device including fin structure with two channel layers and manufacturing method thereof
    Patent number: 9601626
    Abstract: A semiconductor device includes a fin structure protruding from a substrate and having a top face and a first side face and a second side face opposite to the first side face, and first semiconductor layers disposed over the first and second side faces of the fin structure. A thickness in a vertical direction of the first semiconductor layers is smaller than a height of the fin structure.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Yasutoshi Okuno, Chien-Chang Su, Wang-Chun Huang
  • Method for Manufacturing A Dual Work Function Semiconductor Device and the Semiconductor Device Made Thereof
    Publication number: 20160365289
    Abstract: A method for manufacturing a dual work function semiconductor device includes forming a first silicon oxide layer on a substrate and forming a first hafnium-containing dielectric material layer on the first silicon oxide layer. The method further includes forming an aluminum-containing dielectric material layer on the first hafnium-containing dielectric material layer and performing a thermal treatment to intermix the silicon oxide layer, the first hafnium-containing dielectric material layer and the aluminum-containing dielectric material layers. This results in an intermixing dielectric layer containing hafnium, aluminum, silicon, and oxygen. The method further includes forming a first metal-containing conductive layer on the intermixing dielectric layer and patterning the first metal-containing conductive layer and the intermixing dielectric layer, thereby forming a first gate stack in a first region.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 15, 2016
    Inventors: Joshua Tseng, Yasutoshi Okuno, Lars-Ake Ragnarsson, Tom Schram, Stefan Kubicek, Thomas Y. Hoffmann, Naohisa Sengoku
  • Methods for Probing Semiconductor Fins and Determining Carrier Concentrations
    Publication number: 20160268174
    Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.
    Type: Application
    Filed: May 23, 2016
    Publication date: September 15, 2016
    Inventors: Clement Hsingjen Wann, Yasutoshi Okuno, Ling-Yen Yeh, Chi-Yuan Shih, Yuan-Fu Shao, Wei-Chun Tsai
  • SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURE WITH TWO CHANNEL LAYERS AND MANUFACTURING METHOD THEREOF
    Publication number: 20160218217
    Abstract: A semiconductor device includes a fin structure protruding from a substrate and having a top face and a first side face and a second side face opposite to the first side face, and first semiconductor layers disposed over the first and second side faces of the fin structure. A thickness in a vertical direction of the first semiconductor layers is smaller than a height of the fin structure.
    Type: Application
    Filed: January 23, 2015
    Publication date: July 28, 2016
    Inventors: Tung Ying Lee, Yasutoshi Okuno, Chien-Chang Su, Wang-Chun Huang
  • Semiconductor device having high-K gate dielectric layer
    Patent number: 9385208
    Abstract: A semiconductor device includes a substrate and a gate structure over the substrate. The gate structure includes a dielectric portion and an electrode portion that is disposed over the dielectric portion. The dielectric portion includes a carbon-doped high dielectric constant (high-k) dielectric layer over the substrate and a carbon-free high-k dielectric layer adjacent to the electrode portion.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: July 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kun-Yu Lee, Liang-Gi Yao, Yasutoshi Okuno, Clement Hsingjen Wann