Patents by Inventor Yasutoshi Okuno

Yasutoshi Okuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • EPITAXIAL SOURCE/DRAIN AND METHODS OF FORMING SAME
    Publication number: 20200058560
    Abstract: A method for forming an epitaxial source/drain structure in a semiconductor device includes providing a substrate having a plurality of fins extending from the substrate. In some embodiments, a liner layer is formed over the plurality of fins. The liner layer is patterned to expose a first group of fins of the plurality of fins in a first region. In some embodiments, a first epitaxial layer is formed over the exposed first group of fins and a barrier layer is formed over the first epitaxial layer. Thereafter, the patterned liner layer may be removed. In various examples, a second epitaxial layer is selectively formed over a second group of fins of the plurality of fins in a second region.
    Type: Application
    Filed: August 8, 2019
    Publication date: February 20, 2020
    Inventors: Cheng-Long CHEN, Yasutoshi OKUNO, Pang-Yen TSAI
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20200043805
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: receiving a substrate having a first epitaxy region in a first transistor of a first conductive type and a second epitaxy region in a second transistor of a second conductive type; introducing an agent onto the first epitaxy region and the second epitaxy region, wherein the agent is selectively deposited to the second epitaxy region; selectively depositing a first metal layer on the first epitaxy region; and depositing a second metal layer on the first epitaxy region and the second epitaxy region. A semiconductor structure according to the method is also provided.
    Type: Application
    Filed: January 18, 2019
    Publication date: February 6, 2020
    Inventors: SUNG-LI WANG, PENG-WEI CHU, YASUTOSHI OKUNO
  • SEMICONDUCTOR DEVICE AND FABRICATION THEREOF
    Publication number: 20200035787
    Abstract: A semiconductor device includes a first semiconductor fin, a first epitaxial layer, a first alloy layer and a contact plug. The first semiconductor fin is on a substrate. The first epitaxial layer is on the first semiconductor fin. The first alloy layer is on the first epitaxial layer. The first alloy layer is made of one or more Group IV elements and one or more metal elements, and the first alloy layer comprises a first sidewall and a second sidewall extending downwardly from a bottom of the first sidewall along a direction non-parallel to the first sidewall. The contact plug is in contact with the first and second sidewalls of the first alloy layer.
    Type: Application
    Filed: January 18, 2019
    Publication date: January 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li WANG, Mrunal A. KHADERBAD, Yasutoshi OKUNO
  • MEMORY CELL AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20200020699
    Abstract: A memory cell includes a first and second pull up transistor, a first and second pass gate transistor and a metal contact. The first pull up transistor has a first active region extending in a first direction. The first pass gate transistor has a second active region extending in the first direction, and being separated from the first active region in a second direction. The second active region is adjacent to the first active region. The second pass gate transistor is coupled to the second pull up transistor. The metal contact extends in the second direction, and extends from the first active region to the second active region. The metal contact couples drains of the first pull up transistor and the first pass gate transistor. The first and second pass gate transistors and the first and second pull up transistors are part of a four transistor memory cell.
    Type: Application
    Filed: June 28, 2019
    Publication date: January 16, 2020
    Inventors: Hidehiro FUJIWARA, Hung-Jen LIAO, Hsien-Yu PAN, Chih-Yu LIN, Yen-Huei CHEN, Yasutoshi OKUNO
  • Selective High-K Formation in Gate-Last Process
    Publication number: 20200013622
    Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: Yasutoshi Okuno, Teng-Chun Tsai, Ziwei Fang, Fu-Ting Yen
  • Interconnect Structures and Methods of Forming the Same
    Publication number: 20200006224
    Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Inventors: Sung-Li Wang, Yasutoshi Okuno
  • Semiconductor device, interconnection structure and method for forming the same
    Patent number: 10515849
    Abstract: A semiconductor device is provided. The semiconductor device includes a source/drain region, a silicide layer on the source/drain region, an interlayer dielectric (ILD) layer over the silicide layer, and a source drain contact. The source/drain contact has a top portion extending through the ILD layer and a bottom portion embedded in the silicide layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mrunal A. Khaderbad, Yasutoshi Okuno, Pang-Yen Tsai
  • Selective high-K formation in gate-last process
    Patent number: 10515809
    Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yasutoshi Okuno, Teng-Chun Tsai, Ziwei Fang, Fu-Ting Yen
  • Method of providing layout design of SRAM cell
    Patent number: 10510739
    Abstract: A method of providing a layout design of an SRAM cell includes: providing a substrate layout comprising a first oxide diffusion area, a second oxide diffusion area, a first polysilicon layout, and a second polysilicon layout, wherein the first polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area, and the second polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area; forming a first pull-up transistor on the first oxide diffusion area and the first polysilicon layout; forming a first pull-down transistor on the second oxide diffusion area and the first polysilicon layout; forming a second pull-up transistor on the first oxide diffusion area and the second polysilicon layout; and forming a second pull-down transistor on the second oxide diffusion area and second first polysilicon layout.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hidehiro Fujiwara, Tetsu Ohtou, Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Yen-Huei Chen
  • Method for manufacturing a dual work function semiconductor device and the semiconductor device made thereof
    Patent number: 10424517
    Abstract: A method for manufacturing a dual work function semiconductor device includes forming a first silicon oxide layer on a substrate and forming a first hafnium-containing dielectric material layer on the first silicon oxide layer. The method further includes forming an aluminum-containing dielectric material layer on the first hafnium-containing dielectric material layer and performing a thermal treatment to intermix the silicon oxide layer, the first hafnium-containing dielectric material layer and the aluminum-containing dielectric material layers. This results in an intermixing dielectric layer containing hafnium, aluminum, silicon, and oxygen. The method further includes forming a first metal-containing conductive layer on the intermixing dielectric layer and patterning the first metal-containing conductive layer and the intermixing dielectric layer, thereby forming a first gate stack in a first region.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: September 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Joshua Tseng, Yasutoshi Okuno, Lars-Ake Ragnarsson, Tom Schram, Stefan Kubicek, Thomas Y Hoffman, Naohisa Sengoku
  • Replacement Contacts
    Publication number: 20190237364
    Abstract: The present disclosure describes a method of forming a replacement contact. For example, the replacement contact can include a metal with one or more first sidewall surfaces and a top surface. A first dielectric can be formed to abut the one or more first sidewall surfaces of the metal. A second dielectric can be formed over the first dielectric and the top surface of the metal. An opening in the second dielectric can be formed. A metal oxide structure can be selectively grown on the top surface of the metal, where the metal oxide structure has one or more second sidewall surfaces. One or more spacers can be formed to abut the one or more second sidewall surfaces of the metal oxide structure. Further, the metal oxide structure can be removed.
    Type: Application
    Filed: April 8, 2019
    Publication date: August 1, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yee-Chia YEO, Teng-Chun TSAI, Yasutoshi OKUNO
  • Semiconductor device including fin structure with two channel layers and manufacturing method thereof
    Patent number: 10326023
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Chien-Chang Su, Wang-Chun Huang, Yasutoshi Okuno
  • SEMICONDUCTOR DEVICE, INTERCONNECTION STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20190164828
    Abstract: A semiconductor device is provided. The semiconductor device includes a source/drain region, a silicide layer on the source/drain region, an interlayer dielectric (ILD) layer over the silicide layer, and a source drain contact. The source/drain contact has a top portion extending through the ILD layer and a bottom portion embedded in the silicide layer.
    Type: Application
    Filed: March 29, 2018
    Publication date: May 30, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mrunal A. KHADERBAD, Yasutoshi OKUNO, Pang-Yen TSAI
  • Interconnect Structures and Methods of Forming the Same
    Publication number: 20190164887
    Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.
    Type: Application
    Filed: May 31, 2018
    Publication date: May 30, 2019
    Inventors: Sung-Li Wang, Yasutoshi Okuno
  • Contact Plugs for Semiconductor Device and Method of Forming Same
    Publication number: 20190164817
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.
    Type: Application
    Filed: August 24, 2018
    Publication date: May 30, 2019
    Inventors: Mrunal A Khaderbad, Yasutoshi Okuno, Sung-Li Wang, Pang-Yen Tsai, Shen-Nan Lee, Teng-Chun Tsai
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190164965
    Abstract: A semiconductor device comprises a substrate having an N-type field effect transistor (NFET) region and a P-type field effect transistor (PFET) region, a plurality of first nanowires in the PFET region and arranged in a first direction substantially perpendicular to the substrate and a plurality of second nanowires in the NFET region and arranged in the first direction. A composition of the first nanowires is different from a composition of the second nanowires, and one of the first nanowires is substantially aligned with one of the second nanowires in a second direction substantially perpendicular to the first direction.
    Type: Application
    Filed: April 26, 2018
    Publication date: May 30, 2019
    Inventors: Winnie Victoria Wei-Ning CHEN, Meng-Hsuan HSIAO, Tung-Ying LEE, Pang-Yen TSAI, Yasutoshi OKUNO
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190164966
    Abstract: A semiconductor device includes first and second epitaxial structures, first and second top metal alloy layers, and first and second bottom metal alloy layers. The first and second epitaxial structures have different cross sections. The first and second top metal alloy layers are respectively in contact with the first and second epitaxial structures. The first and second bottom metal alloy layers are respectively in contact with the first and second epitaxial structures and respectively under the first and second top metal alloy layers. The first top metal alloy layer and the first bottom metal alloy layer are made of different materials.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 30, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li WANG, Pang-Yen TSAI, Yasutoshi OKUNO
  • Selective High-K Formation in Gate-Last Process
    Publication number: 20190148151
    Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.
    Type: Application
    Filed: July 2, 2018
    Publication date: May 16, 2019
    Inventors: Yasutoshi Okuno, Teng-Chun Tsai, Ziwei Fang, Fu-Ting Yen
  • Replacement contacts
    Patent number: 10256143
    Abstract: The present disclosure describes a method of forming a replacement contact. For example, the replacement contact can include a metal with one or more first sidewall surfaces and a top surface. A first dielectric can be formed to abut the one or more first sidewall surfaces of the metal. A second dielectric can be formed over the first dielectric and the top surface of the metal. An opening in the second dielectric can be formed. A metal oxide structure can be selectively grown on the top surface of the metal, where the metal oxide structure has one or more second sidewall surfaces. One or more spacers can be formed to abut the one or more second sidewall surfaces of the metal oxide structure. Further, the metal oxide structure can be removed.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: April 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yee-Chia Yeo, Teng-Chun Tsai, Yasutoshi Okuno
  • METHOD OF FABRICATING GATE OXIDE OF SEMICONDUCTOR DEVICE
    Publication number: 20190096682
    Abstract: A method of fabricating a semiconductor device includes forming a semiconductor fin comprising a channel region for a fin field effect transistor (finFET). A gate oxide layer is then formed on the channel. The gate oxide layer is treated with a nitrogen containing agent so as to form a nitrogenous layer and an interfacial layer. The nitrogenous layer is then removed. A high-k dielectric layer is formed on the interfacial layer. A metal gate is formed on the high-k dielectric layer. The nitrogenous layer is removed by rinsing the semiconductor fin with deionized water. The gate oxide and interfacial layer contains the same material.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Andrew Joseph KELLY, Yusuke ONIKI, Yasutoshi OKUNO, Ta-Chun MA