Patents by Inventor Yasuyuki Baba
Yasuyuki Baba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180175055Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: February 12, 2018Publication date: June 21, 2018Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Publication number: 20180108418Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: October 23, 2017Publication date: April 19, 2018Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Patent number: 9893078Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: GrantFiled: February 24, 2015Date of Patent: February 13, 2018Assignee: Toshiba Memory CorporationInventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
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Publication number: 20170309634Abstract: A semiconductor memory device comprises a memory block including conductive layers at different levels from a substrate and separated from each other by a first insulation material. A memory pillar extends through the first conductive layers. A hookup region is adjacent to the memory block and includes conductive layers stacked on the substrate at levels from the substrate that corresponds to the conductive layers in the memory block. An isolation region is between the memory block and the hookup region and includes first insulating layers of a second insulating material different than the first insulating material. Each first insulating layer is at a level from the substrate that corresponds to one of the first conductive layers and each first insulating layer is between one of the conductive layers in the memory block and one of the conductive layers in hookup region.Type: ApplicationFiled: April 18, 2017Publication date: October 26, 2017Inventors: Mitsuhiro NOGUCHI, Yoshitaka KUBOTA, Yasuyuki BABA
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Patent number: 9799403Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: GrantFiled: June 6, 2016Date of Patent: October 24, 2017Assignee: Toshiba Memory CorporationInventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
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Patent number: 9768189Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: GrantFiled: April 7, 2016Date of Patent: September 19, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroshi Shinohara, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
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Publication number: 20170213845Abstract: A semiconductor memory device includes a plurality of wiring layers formed on a substrate, one or more first pillars penetrating through the wiring layers on a memory region of the substrate and in contact with the substrate, a plurality of memory transistors being formed at portions of each of the one or more first pillars that penetrate the wiring layers, and one or more second pillars penetrating through at least one of the wiring layers on a peripheral region of the substrate and in contact with the substrate. Each of the first and second pillars includes a semiconductor portion, a first insulating layer formed around the semiconductor portion, a charge accumulation layer formed around the first insulating layer, and a second insulating layer formed around the charge accumulation layer.Type: ApplicationFiled: August 10, 2016Publication date: July 27, 2017Inventor: Yasuyuki BABA
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Patent number: 9620519Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell array including a first selection gate, word lines and a second selection gate stacked above a semiconductor substrate, and a memory pillar disposed through the first selection gate, word lines and second selection gate, a hookup region disposed adjacent to the memory cell array region in a first direction, and a dummy region disposed outside the memory cell array region and the hookup region, the dummy region including dummy word lines, each provided at the same layer as the associated word line.Type: GrantFiled: September 2, 2015Date of Patent: April 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuyuki Baba, Kazuichi Komenaka, Hirofumi Inoue
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Publication number: 20160358659Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: June 6, 2016Publication date: December 8, 2016Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Publication number: 20160260722Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell array including a first selection gate, word lines and a second selection gate stacked above a semiconductor substrate, and a memory pillar disposed through the first selection gate, word lines and second selection gate, a hookup region disposed adjacent to the memory cell array region in a first direction, and a dummy region disposed outside the memory cell array region and the hookup region, the dummy region including dummy word lines, each provided at the same layer as the associated word line.Type: ApplicationFiled: September 2, 2015Publication date: September 8, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Yasuyuki BABA, Kazuichi KOMENAKA, Hirofumi INOUE
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Patent number: 9437300Abstract: A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.Type: GrantFiled: August 26, 2014Date of Patent: September 6, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hideyuki Kamata, Toshifumi Minami, Teppei Higashitsuji, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara
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Publication number: 20160218109Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: ApplicationFiled: April 7, 2016Publication date: July 28, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi SHINOHARA, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
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Patent number: 9361988Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: GrantFiled: August 26, 2014Date of Patent: June 7, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
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Patent number: 9337145Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: GrantFiled: March 10, 2015Date of Patent: May 10, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Shinohara, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
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Publication number: 20160071793Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: ApplicationFiled: March 10, 2015Publication date: March 10, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi SHINOHARA, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Toshifumi MINAMI, Hiroyuki MAEDA, Shinji SAITO, Hideyuki KAMATA
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Publication number: 20160071870Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: February 24, 2015Publication date: March 10, 2016Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Patent number: 9252097Abstract: The semiconductor memory device comprises a plurality of first wiring lines extending in a first direction, a plurality of second wiring lines extending in a second direction crossing the first direction, and a memory cell array comprising memory cells, the memory cells being connected to the first wiring lines and second wiring lines in the crossing portions of the first and second wiring lines. A plurality of first dummy-wiring-line regions are formed in the peripheral area around the memory cell array. A contact is formed in the peripheral area, the contact extending in a third direction perpendicular to the first and second directions. A plurality of second dummy-wiring-line regions are formed in the periphery of the contact. The mean value of the areas of the second dummy-wiring-line regions is less than the mean value of the areas of the first dummy-wiring-line regions.Type: GrantFiled: August 30, 2012Date of Patent: February 2, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Yasuyuki Baba
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Publication number: 20150262685Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: August 26, 2014Publication date: September 17, 2015Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Publication number: 20150262669Abstract: A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.Type: ApplicationFiled: August 26, 2014Publication date: September 17, 2015Inventors: Hideyuki KAMATA, Toshifumi MINAMI, Teppei HIGASHITSUJI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA
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Patent number: 8723157Abstract: A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon.Type: GrantFiled: September 18, 2013Date of Patent: May 13, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiko Yamamoto, Yasuyuki Baba, Takuya Konno