Patents by Inventor Yasuyuki Baba
Yasuyuki Baba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8648467Abstract: A method of manufacturing a semiconductor memory device according to the embodiment includes: forming a first stacked-structure; forming a first stripe part and a first hook part at the first stacked-structure; forming a second stacked-structure on the first stacked-structure; forming a second stripe part and a second hook part at the second stacked-structure; repeating the above-described four steps for a certain number of times; and forming a contact plug contacting the first or second hook parts. The etching is conducted to remove the first stacked-structure in a region at which the second hook part is to be formed in the second stacked-structure higher than the first stacked-structure by one layer. The etching is conducted to remove the second stacked-structure in a region at which the first hook part is to be formed in the first stacked-structure higher than the second stacked-structure by one layer.Type: GrantFiled: April 27, 2012Date of Patent: February 11, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Yasuyuki Baba
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Publication number: 20140016398Abstract: A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon.Type: ApplicationFiled: September 18, 2013Publication date: January 16, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kazuhiko Yamamoto, Yasuyuki Baba, Takuya Konno
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Publication number: 20130249113Abstract: The semiconductor memory device comprises a plurality of first wiring lines extending in a first direction, a plurality of second wiring lines extending in a second direction crossing the first direction, and a memory cell array comprising memory cells, the memory cells being connected to the first wiring lines and second wiring lines in the crossing portions of the first and second wiring lines. A plurality of first dummy-wiring-line regions are formed in the peripheral area around the memory cell array. A contact is formed in the peripheral area, the contact extending in a third direction perpendicular to the first and second directions. A plurality of second dummy-wiring-line regions are formed in the periphery of the contact. The mean value of the areas of the second dummy-wiring-line regions is less than the mean value of the areas of the first dummy-wiring-line regions.Type: ApplicationFiled: August 30, 2012Publication date: September 26, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yasuyuki BABA
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Publication number: 20120299063Abstract: A method of manufacturing a semiconductor memory device according to the embodiment includes: forming a first stacked-structure; forming a first stripe part and a first hook part at the first stacked-structure; forming a second stacked-structure on the first stacked-structure; forming a second stripe part and a second hook part at the second stacked-structure; repeating the above-described four steps for a certain number of times; and forming a contact plug contacting the first or second hook parts. The etching is conducted to remove the first stacked-structure in a region at which the second hook part is to be formed in the second stacked-structure higher than the first stacked-structure by one layer. The etching is conducted to remove the second stacked-structure in a region at which the first hook part is to be formed in the first stacked-structure higher than the second stacked-structure by one layer.Type: ApplicationFiled: April 27, 2012Publication date: November 29, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Yasuyuki BABA
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Patent number: 8228712Abstract: A semiconductor memory device includes a memory cell array configured as an arrangement of memory cells each arranged between a first line and a second line and each including a variable resistor. A control circuit controls a voltage applied to the first line or the second line. A current limiting circuit limits a current flowing through the first line or the second line to a certain upper limit or lower. In a case where a writing operation or an erasing operation to a memory cell is implemented a plural number of times repeatedly, the current limiting circuit sets the upper limit in the writing operation or erasing operation of the p-th time higher than the upper limit in the writing operation or erasing operation of the q-th time (q<p).Type: GrantFiled: March 17, 2010Date of Patent: July 24, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Yasuyuki Baba
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Patent number: 8222677Abstract: A semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contact plugs extending in the stack direction of the cell array layers to connect between the first lines, between the second lines, between the first or second line and the semiconductor substrate, or between the first or second line and another metal line, in the cell array layers. The first or second line in a certain one of the cell array layers has a contact connector making contact with both sides of the contact plug.Type: GrantFiled: March 6, 2009Date of Patent: July 17, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yasuyuki Baba, Hiroyuki Nagashima
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Patent number: 7967787Abstract: A gastrostomy tube extension device which can facilitate insertion or removal of a gastrostomy tube by making the degree of extension of the gastrostomy tube constant. A gastrostomy tube extension device used for inserting and taking out a gastrostomy tube into/from a hole formed on a patient's abdomen, the gastrostomy tube including an outer fixing member to be installed on the skin surface side, an inner fixing member installed on the inner surface side of the stomach wall, and a tube member for connecting the outer fixing member and the inner fixing member and the gastrostomy tube extension device comprising a rod and an engaging member. The rod has a rod-shaped member which can push the center of the distal end of the inner fixing member with its distal portion toward the distal end, and with a plurality of engaging step portions formed on the proximal portion.Type: GrantFiled: April 26, 2005Date of Patent: June 28, 2011Assignee: Tyco Healtcare Group LPInventors: Katsuki Nagata, Yasuyuki Baba
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Publication number: 20110051493Abstract: A semiconductor memory device includes a memory cell array configured as an arrangement of memory cells each arranged between a first line and a second line and each including a variable resistor. A control circuit controls a voltage applied to the first line or the second line. A current limiting circuit limits a current flowing through the first line or the second line to a certain upper limit or lower. In a case where a writing operation or an erasing operation to a memory cell is implemented a plural number of times repeatedly, the current limiting circuit sets the upper limit in the writing operation or erasing operation of the p-th time higher than the upper limit in the writing operation or erasing operation of the q-th time (q<p).Type: ApplicationFiled: March 17, 2010Publication date: March 3, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yasuyuki BABA
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Publication number: 20100213433Abstract: A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon.Type: ApplicationFiled: July 24, 2009Publication date: August 26, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Kazuhiko YAMAMOTO, Yasuyuki BABA, Takuya KONNO
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Publication number: 20100032725Abstract: A semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contact plugs extending in the stack direction of the cell array layers to connect between the first lines, between the second lines, between the first or second line and the semiconductor substrate, or between the first or second line and another metal line, in the cell array layers. The first or second line in a certain one of the cell array layers has a contact connector making contact with both sides of the contact plug.Type: ApplicationFiled: March 6, 2009Publication date: February 11, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yasuyuki BABA, Hiroyuki NAGASHIMA
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Patent number: 7608488Abstract: A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array region of said first semiconductor device so as to be a predetermined height, by performing etching treatment under predetermined conditions using a first etching mask having a first opening for exposing the entirety of said first memory cell array region, and forming the height of second element-isolating insulating films of second memory cell array region and part of peripheral circuit region of said second semiconductor device so as to be the predetermined height, by performing etching treatment under said predetermined conditions using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for exType: GrantFiled: October 18, 2007Date of Patent: October 27, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yasuyuki Baba, Susumu Yoshikawa
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Publication number: 20080258201Abstract: A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array region of said first semiconductor device so as to be a predetermined height, by performing etching treatment under predetermined conditions using a first etching mask having a first opening for exposing the entirety of said first memory cell array region, and forming the height of second element-isolating insulating films of second memory cell array region and part of peripheral circuit region of said second semiconductor device so as to be the predetermined height, by performing etching treatment under said predetermined conditions using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for exType: ApplicationFiled: October 18, 2007Publication date: October 23, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuyuki BABA, Susumu Yoshikawa
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Publication number: 20080255522Abstract: To provide a medical needle puller that allows an easy pulling operation as well as safety improvement. The engaging stepped part 14 was formed at the back side of the puncture part 12 in the medical needle 10 in which the connection part 13 for connecting the drainage tube 16 was formed at the rear end part and the puncture part 12 was formed at the tip part. Furthermore, the puller 20 to which the medical needle 10 is attached was provided with the needlepoint coating part 21 coating the puncture part 12 and the engaging narrow part 25 engaging the engaging stepped part 14. In addition, the puller 20 was provided with the grippers 22a, 22b for pulling out the medical needle 10 together with the puller 20 from the wound site by hand.Type: ApplicationFiled: October 5, 2007Publication date: October 16, 2008Applicant: TYCO HEALTHCARE GROUP LPInventors: Akira Itoh, Yasuyuki Baba, Masanori Makino, Kazuhiro Koike
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Publication number: 20080208208Abstract: To provide a gastrostomy tube extension device which can facilitate insertion or removal of a gastrostomy tube by making the degree of extension of the gastrostomy tube constant. [Means for Resolution] A gastrostomy tube extension device 20 used for inserting and taking out a gastrostomy tube 10 into/from a hole 33 formed on a patient's abdomen, the gastrostomy tube 10 including an outer fixing member 10a to be installed on the skin surface side, an inner fixing member 10c installed on the inner surface side of the stomach wall, and a tube member 10b for connecting the outer fixing member 10a and the inner fixing member 10c, and the gastrostomy tube extension device comprising a rod 21 and an engaging member 22. The rod 21 has a rod-shaped member which can push the center of the distal end of the inner fixing member 10c with its distal portion toward the distal end, and with a plurality of engaging step portions 24a are formed on the proximal portion.Type: ApplicationFiled: April 26, 2005Publication date: August 28, 2008Applicant: SHERWOOD SERVICES AGInventors: Katsuki Nagata, Yasuyuki Baba
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Patent number: 6740183Abstract: A method for manufacturing a multi-layered ceramic substrate which enables to remove a shrinkage suppression sheet without damaging the multi-layered substrate. The shrinkage suppression sheets are formed on both faces of unfired laminated green sheets, and then the laminated green sheets are fired. For removing the shrinkage suppression sheets on both faces of the multi-layered ceramic substrate 2 after sintering, water, ceramic powder, or water and ceramic powder mixture is sprayed together with compressed air.Type: GrantFiled: April 24, 2000Date of Patent: May 25, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shigetoshi Segawa, Hiroshi Ochi, Yasuyuki Baba, Osamu Shiraishi, Masao Konishi
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Patent number: 6598292Abstract: A manufacturing method of a circuit board comprises the steps of: (a) feeding a printing stage having a porous member comprising a porous plate and a porous sheet, the porous sheet is composed of 90 wt % to 98 wt % of cellulose; (b) placing a plate for the circuit board having a pierced hole above the porous member; and (c) filling a conductive material in the pierced hole from an upper side of the plate for circuit board by sucking the porous member at a prescribed vacuum pressure from a back of the porous member.Type: GrantFiled: July 13, 2000Date of Patent: July 29, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shigetoshi Segawa, Yasuyuki Baba, Katsuyoshi Ishikawa, Kazuhiko Ihara
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Patent number: 6244592Abstract: The present invention provides a sheet feeding apparatus for a corrugated fiberboard box making machine, which has front stops disposed at two locations spaced in the width direction (transverse direction) to true up the front edges of stacked corrugated fiberboard sheets and is constructed so as to feed a lowermost corrugated fiberboard sheet successively from the front end side of the front stop, characterized in that the front stops at the two locations are constructed so as to be movable in the longitudinal direction in such a manner as to be capable of supporting the corrugated fiberboard sheets while tilting the front edges thereof obliquely in the longitudinal direction.Type: GrantFiled: May 27, 1999Date of Patent: June 12, 2001Assignee: Mitsubishi Heavy Industries, Ltd.Inventors: Yasuyuki Baba, Osamu Hatano
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Patent number: 6230597Abstract: A rotary die cutter in accordance with the present invention has frames 1 for rotatably supporting a die cut cylinder 20 and an anvil cylinder 21 via a bearing 22, and is configured so that oil is circulated in the die cut cylinder 20 and/or the anvil cylinder 21. Also, another rotary die cutter in accordance with the present invention has frames 20 for rotatably supporting a die cut cylinder 3 and an anvil cylinder 4 via a bearing 21, and is configured so that a cooled lubricating oil 23 is supplied to the bearing 21.Type: GrantFiled: March 17, 1999Date of Patent: May 15, 2001Assignee: Mitsubishi Heavy Industries, Ltd.Inventors: Yasuyuki Baba, Kunio Niuchi
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Patent number: D558341Type: GrantFiled: March 19, 2007Date of Patent: December 25, 2007Assignee: Tyco Healthcare Group LPInventors: Norifumi Fujiwara, Yasuyuki Baba, Nobuaki Suzuki, Akira Itoh
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Patent number: D558342Type: GrantFiled: March 19, 2007Date of Patent: December 25, 2007Assignee: Tyco Healthcare Group LPInventors: Norifumi Fujiwara, Yasuyuki Baba, Nobuaki Suzuki, Akira Itoh