Abstract: A main semiconductor device element is SiC-MOSFETs with a trench gate structure, the main semiconductor device element having main MOS regions responsible for driving the MOSFETs and main SBD regions that are regions responsible for SBD operation. The main MOS regions and the main SBD regions are adjacent to one another and each pair of a main MOS region and a main SBD region adjacent thereto share one trench. In the main SBD regions, first and second p-type regions, and Schottky electrodes at the front surface of the semiconductor substrate and forming Schottky junctions with an n?-type drift region are provided. The first p-type regions are provided along sidewalls of the trenches, in contact with the first p+-type regions at the bottoms of the trenches. The second p-type regions are provided between the first p-type regions and the Schottky electrodes, and are electrically connected to these regions.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type provided on a front surface of a semiconductor substrate of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; and a gate electrode having a striped-shape and provided on a gate insulating film. The silicon carbide semiconductor device further includes a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region; a step film provided on the first electrode; a plating film provided on the first electrode and the step film; and a solder on the plating film. The step film is provided on the first electrode on which the solder and the plating film are provided, the step film being provided so as to be embedded in grooves formed on the first electrode.

Abstract: A region of a portion directly beneath an OC pad is a sensing effective region in which unit cells of a current sensing portion are disposed. A p-type low-dose region is provided on a front surface of a semiconductor substrate and surrounds a periphery of the sensing effective region. The p-type low-dose region is fixed at an electric potential of a source pad of a main semiconductor element. The p-type low-dose region is disposed to be separated from a p-type base region of the sensing effective region by an n?-type region between the p-type low-dose region and the sensing effective region. A total dose of impurities in the p-type low-dose region is lower than a total dose of impurities in a p-type region of a front side of a semiconductor substrate in a main effective region in which unit cells of the main semiconductor element are disposed.

Abstract: A semiconductor device includes an N-type silicon carbide layer, a P-type region, an N-type source region, a P-type contact region, a gate insulating film, a gate electrode, and a source electrode on the front surface side of an N-type silicon carbide substrate. A drain electrode is located on the back surface of the N-type silicon carbide substrate. A life time killer introduction region is located along an entire interface of the N-type silicon carbide layer and the bottom face of the P-type region. The life time killer is introduced by implanting helium or protons from the back surface side of the N-type silicon carbide substrate after forming a surface structure of an element on the front surface side of the N-type silicon carbide substrate and before forming the drain electrode.

Abstract: A main semiconductor device element has first and second p+-type high-concentration regions that mitigate electric field applied to bottoms of trenches. The first p+-type high-concentration regions are provided separate from p-type base regions, face the bottoms of the trenches in a depth direction, and extend in a linear shape in a first direction that is a same direction in which the trenches extend. Between adjacent trenches of the trenches, the second p+-type high-concentration regions are provided scattered in the first direction, separate from the first p+-type high-concentration regions and the trenches and in contact with the p-type base regions. Between the second p+-type high-concentration regions adjacent to one another in the first direction, n-type current spreading regions or n+-type high-concentration regions having an impurity concentration higher than that of the n-type current spreading regions are provided in contact with the second p+-type high-concentration regions.

Abstract: A semiconductor device including a semiconductor substrate, a first semiconductor layer provided on a main surface of the semiconductor substrate, a second semiconductor layer selectively provided on a surface of the first semiconductor layer, a plurality of first and second semiconductor regions selectively provided in the second semiconductor layer at a surface thereof, and a plurality of trenches provided in a striped pattern that extends in a first direction.

Abstract: A main semiconductor device element is a vertical MOSFET with a trench gate structure, containing silicon carbide as a semiconductor material, and having first and second p+-type regions that mitigate electric field applied to bottoms of trenches. The first p+-type regions are provided separate from the p-type base regions and face the bottoms of the trenches in a depth direction. The first p+-type regions are disposed at an interval that is at most 1.0 ?m, in a first direction that is a direction in which gate electrodes extend. The second p+-type regions are provided between adjacent trenches of the trenches, separate from the first p+-type regions and the trenches, and in contact with the p-type base regions. In the first direction that is the direction in which the trenches, the second p+-type regions extend in a linear shape having a length that is substantially equal to that of the trenches.

Abstract: A semiconductor device having, in a main non-operating region that is free of unit cells of a main semiconductor element, a gate insulating film and a gate electrode of a current sensing portion extending on a front surface of a semiconductor substrate, to thereby form a planar gate structure. A gate capacitance of the planar gate structure is a gate capacitance of the current sensing portion. Directly beneath the planar gate structure, at the front surface of the semiconductor substrate, a structure is provided in which, from a front side of the semiconductor substrate, a p-type region, an n-type region, and a p-type region are stacked, whereby electric field is not applied to the extended portions of the gate insulating film.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type on a substrate of the first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a first semiconductor region of the first conductivity type. The semiconductor device further includes a gate electrode provided in a plurality of trenches via gate insulating films, a protruding portion disposed on the second semiconductor layer at a bridge area between two adjacent ones of the trenches in a direction orthogonal to the trenches, an interlayer insulating film provided on the gate electrode, and having contact holes that form a striped pattern, a first electrode on the interlayer insulating film and in the contact holes, a plating film provided in a plating area, and a solder on the plating film.

Abstract: A region of a portion directly beneath an OC pad is a sensing effective region where unit cells of a current sensing portion are disposed. Directly beneath the OC pad, a region surrounding a periphery of the sensing effective region is a sensing non-operating region in which no unit cells of the current sensing portion are disposed. In the sensing non-operating region, a first p-type base region that floats is provided in a surface region of the front surface of the semiconductor substrate and is separated from a second p-type base region of the sensing effective region by an n?-type region that surrounds a periphery of the sensing effective region. The n?-type region has a surface area that is greater than that of the sensing effective region. A distance between the first and the second p-type base regions is at least 0.1 ?m and is as small as possible.

Abstract: A semiconductor device has first second-conductivity-type high-concentration regions, second second-conductivity-type high-concentration regions, third second-conductivity-type high-concentration regions, and fourth second-conductivity-type high-concentration regions. The first connecting regions each connect a portion of each of the first second-conductivity-type high-concentration regions and a portion of each of the second second-conductivity-type high-concentration regions. The second connecting regions each connect a portion of each of the third second-conductivity-type high-concentration regions and a portion of each of the fourth second-conductivity-type high-concentration regions. A ratio of a mathematical area of the first connecting regions to a mathematical area of the second second-conductivity-type high-concentration regions is greater than a ratio of a mathematical area of the second connecting regions to a mathematical area of the fourth second-conductivity-type high-concentration regions.

Abstract: Unit cells of a current sensing portion are disposed in a sensing effective region of a main non-operating region. In a sensing non-operating region of the main non-operating region excluding the sensing effective region, an n?-type region that surrounds a periphery of the sensing effective region is disposed in a surface region of the front surface of the semiconductor substrate. In the main non-operating region, a p-type base region disposed in a surface region of the front surface of the semiconductor substrate opposes the sensing effective region across the n?-type region. The p-type base region is fixed at a source potential of the main semiconductor element 11. A field insulating film on the front surface of the semiconductor substrate is thicker at a portion that covers the n?-type region that in other portions.

Abstract: In an effective region of an active region, a main semiconductor element and a source pad thereof are disposed. A non-operating region of the active region excludes the effective region and is a high-function region in which a gate pad of the main semiconductor element and other electrode pads are disposed. An edge termination region and the electrode pads are separated by an interval equivalent to at least a width of one unit cell of the main semiconductor element. In the high-function region, at a border of the edge termination region, a lead-out electrode is provided on a front surface of a semiconductor substrate. The lead-out electrode has a function of leading out displacement current that flows to the high-function region from the edge termination region when the main semiconductor element is OFF. Thus, destruction at the edge termination region may be suppressed.

Abstract: A semiconductor device includes a first MOS structure portion that includes, as its elements, a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first second-semiconductor-layer of a second conductivity type, first semiconductor regions of the first conductivity type, and first gate insulating films, and a second MOS structure portion that includes, as its elements, the substrate, the first semiconductor layer, a second second-semiconductor-layer, second first-semiconductor-regions of the first conductivity type, and second gate insulating films. First and second portions include all of the elements of the first and second MOS structure portions other than the first and second first-semiconductor-regions and the first and second gate insulating films, respectively. A structure of one of the elements of the first portion is not identical to a structure of a corresponding element of the second portion.

Abstract: A semiconductor device having, in a plan view thereof, an active region and a termination region that surrounds a periphery of the active region. The device includes a semiconductor substrate containing a wide bandgap semiconductor, a first-conductivity-type region provided in the semiconductor substrate, spanning from the active region to the termination region, a plurality of second-conductivity-type regions provided between the first-conductivity-type region and the first main surface of the semiconductor substrate in the active region, a first electrode provided on a first main surface of the semiconductor substrate and electrically connected to the second-conductivity-type regions, a second electrode provided on the second main surface of the semiconductor substrate and electrically connected to the first-conductivity-type region, and a lifetime killer region provided in the first-conductivity-type region and spanning from the active region to the termination region.

Abstract: In an effective region of an active region, main semiconductor elements that are vertical MOSFETs and a source pad of the main semiconductor elements are provided. In a non-operating region of the active region, a gate pad of the main semiconductor elements is provided on a front surface of a semiconductor substrate. Directly beneath the gate pad, in a surface region of the front surface of the semiconductor substrate, a p-type region is provided spanning the non-operating region of the active region overall. The p-type region of the non-operating region of the active region is electrically connected to the source pad and forms a parasitic diode by a pn junction with an n?-type drift region when the main semiconductor elements are OFF. The p-type region of the non-operating region of the active region has a rectangular planar shape with rounded or chamfered corner portions in a planar view.

Abstract: A semiconductor device includes an active region configured by a first MOS structure region and a second MOS structure region, a gate ring region surrounding a periphery of the active region, a first ring region surrounding a periphery of the gate ring region, a second ring region surrounding a periphery of the first ring region, and a termination region surrounding a periphery of the second ring region. The semiconductor device has first first-electrodes in the first MOS structure region, second first-electrodes in the second MOS structure region, a third first-electrode in the first ring region, and a fourth first-electrode in the second ring region. The third first-electrode has a potential equal to that of the second first-electrodes, and the fourth first-electrode has a potential equal to that of the first first-electrodes.

Abstract: A semiconductor device, comprising a first MOS structure region, a second MOS structure region, a first temperature sensing region, and a second temperature sensing region. The first temperature sensing region is provided in a region through which a main current of the semiconductor device passes when the first MOS structure region is in an ON state. The second temperature sensing region is provided in a region through which the main current of semiconductor device passes when the second MOS structure region is in the ON state.

Abstract: In an edge termination region, a second gate runner for a current sensor is formed between a first gate runner for a main semiconductor device and an active region. The second gate runner surrounds the periphery of the active region in a substantially rectangular shape having an opening. One end of the second gate runner is connected to all of the gate electrodes of the current sensor, and the other end is connected to the first gate runner at between a gate pad and an OC pad. This makes it possible to increase the gate capacitance of the current sensor as the current sensor switches ON and OFF when a pulse-shaped gate voltage is applied to the gate pad by an amount proportional to the surface area of the second gate runner.

Abstract: A semiconductor device including a semiconductor substrate, a first semiconductor layer provided on a main surface of the semiconductor substrate, a second semiconductor layer selectively provided on a surface of the first semiconductor layer, a plurality of first and second semiconductor regions selectively provided in the second semiconductor layer at a surface thereof, and a plurality of trenches provided in a striped pattern that extends in a first direction.