Abstract: Trenches and n+ high impurity concentration regions are formed in a first principal surface side of a silicon carbide semiconductor substrate. In the n+ high impurity concentration regions, third n-type regions that respectively surround first p+ base regions contacting a p-type base layer and have a higher impurity concentration than the n+ high impurity concentration regions, as well as fourth n-type regions that respectively surround second p+ base regions formed at the bottoms of the trenches and also have a higher impurity concentration than the n+ high impurity concentration regions, are formed.

Abstract: A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer.

Abstract: A semiconductor device includes an N-type silicon carbide substrate, an N-type silicon carbide layer formed on the N-type silicon carbide substrate, a P-type region selectively formed in a surface layer of the N-type silicon carbide layer, an N-type source region formed in the P-type region, a P contact region formed in the P-type region, a gate insulating film formed on a portion of a region from the N-type source region, through the P-type region, to the N-type silicon carbide layer, a gate electrode formed on the gate insulating film, an interlayer insulating film covering the gate electrode, and a first source electrode electrically connected to a surface of the P contact region and the N-type source region. An end of the interlayer insulating film covering the gate electrode has a slope of a predetermined angle.

Abstract: A silicon carbide semiconductor device includes a semiconductor substrate of a first conductivity type; an active region in which a main current flows provided on the semiconductor substrate; a termination region disposed outside of the active region and in which a voltage withstanding structure is formed; and a damaged region disposed outside the termination region and in which crystallinity is impaired, the damaged region being exposed at a cut surface that is formed when singulation is performed.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a first semiconductor layer, a first semiconductor region, a second semiconductor layer, a second semiconductor region, a third semiconductor region, a fourth semiconductor sub-region, a first electrode, a gate insulating film, a gate electrode, and second electrode. At a corner part of an active region in which a main current flows, a fifth semiconductor sub-region is provided. An impurity concentration of the fifth semiconductor sub-region is higher than an impurity concentration of the second semiconductor layer.

Abstract: A semiconductor device includes an n+-type source region having an impurity concentration higher than that of an n-type source region, formed in a surface layer of a p-type SiC layer and a p-type base region, farther on an outer side than the n-type source region, and contacting the n-type source region; an n-type region and an n+-type region having an impurity concentration higher than that of the n?-type SiC layer, formed in a portion of the n?-type SiC layer between p-type base regions and p-type SiC layers; and a second n-type region under the p-type base region and of a size smaller than that of the p-type base region, whereby low on-resistance and precision of the threshold voltage Vth are enhanced, increasing quality and enabling improved resistance to dielectric breakdown of the gate insulating film and resistance to breakdown.

Abstract: A semiconductor device, including a substrate, a deposition layer deposited on the substrate, a semiconductor region selectively provided in the deposition layer, a semiconductor layer provided on the deposition layer and the semiconductor region, a first region and a second region selectively provided in the semiconductor layer, a gate electrode provided on the second region and the semiconductor layer via a gate insulating film, a source electrode in contact with the semiconductor layer and the second region, an interlayer insulating film covering the gate electrode, a drain electrode provided on the substrate, a plating film selectively provided on the source electrode at portions thereof on which the protective film is not provided, and a pin-shaped electrode connected to the plating film via solder. The second region is not formed directly beneath a portion where the plating film, the protective film and the source electrode are in contact with one another.

Abstract: A semiconductor device includes a wide-bandgap semiconductor substrate of a first conductivity type, a wide-bandgap semiconductor deposition layer of the first conductivity type, semiconductor regions of a second conductivity type, a wide-bandgap semiconductor layer of the second conductivity type, first regions of the first conductivity type, and second regions of the first conductivity type. The width w of a plating film formed on a source electrode of the semiconductor device is greater than or equal to 10 ?m. Beneath the plating film, the wide-bandgap semiconductor layer is formed on the surface of one of the semiconductor regions of the second conductivity type.

Abstract: A recess where an edge termination region is lower than an active region is disposed on a silicon carbide base body and an n?-type silicon carbide layer is exposed at a bottom of the recess. In the portion of the n?-type silicon carbide layer exposed at the bottom of the recess, first and second JTE regions configuring a JTE structure are disposed. The first JTE region is disposed from the bottom of the recess, along a side wall and covers a bottom corner portion of the recess. The first JTE region overlaps an outermost first p-type base region at the bottom corner portion. The first JTE region has an impurity concentration that is highest at the portion overlapping the first p-type base region and distribution of the impurity concentration in a depth direction peaks at a portion deeper than the bottom of the recess.

Abstract: When hydrogen penetrates in to the semiconductor device, a gate voltage threshold of a gate structure (Vth) is shifted. Penetrating of hydrogen into the semiconductor device from the edge termination structure section which is positioned at an end portion of the semiconductor device is prevented. To provide a semiconductor device comprising a semiconductor substrate in which an active region and an edge termination structure section which is provided around the active region are provided, a first lower insulating film which is provided in the edge termination structure section on the semiconductor substrate, and a first protective film which is provided on the first lower insulating film, and is electrically insulated from the semiconductor substrate, and occludes hydrogen.

Abstract: A current sensing part that detects overcurrent of a main semiconductor element is arranged on a same silicon carbide base as the main semiconductor element. An isolating part is arranged between the main semiconductor element and the current sensing part. The isolating part has a function of suppressing interference of the main semiconductor element and the current sensing part at the silicon carbide base. The isolating part is constituted by a trench provided a predetermined depth from a front surface of the silicon carbide base. An insulating film is provided in the trench, along inner walls of the trench. A poly-silicon layer is provided on the insulating film. With such a configuration, decreases in breakdown voltage of the current sensing part may be prevented.

Abstract: A main semiconductor element and a temperature sensing part are arranged on a single silicon carbide base. The main semiconductor element is a vertical MOSFET and the temperature sensing part is a horizontal diode. An anode region of the temperature sensing part and an n+-type source region and a p+-type contact region of the main semiconductor element are connected by wiring by an anode electrode on a front surface of the silicon carbide base. The temperature sensing part, when the main semiconductor element is ON, is forward biased by drift current flowing in the main semiconductor element. The temperature sensing part, for example, is a poly-silicon diode constituted by a p-type poly-silicon layer and an n-type poly-silicon layer arranged on the front surface of the silicon carbide base. With such configuration, a semiconductor device having high reliability may be provided.

Abstract: A semiconductor device includes on an n-type semiconductor substrate of silicon carbide, an n-type semiconductor layer, a p-type base region, an n-type source region, a p-type contact region, a gate insulating film, a gate electrode, and a source electrode. The semiconductor device has a drain electrode on a back surface of the semiconductor substrate. On a surface of the gate electrode, an interlayer insulating film is disposed. The interlayer insulating film has plural layers among which, one layer is formed by a silicon nitride film. With such a structure, degradation of semiconductor device properties are suppressed. Further, increases in the number of processes at the time of manufacturing are suppressed.

Abstract: A semiconductor device of an embodiment includes a p+-type region selectively disposed in a surface of an n-type silicon carbide epitaxial layer disposed on an n+-type silicon carbide substrate, an element structure that includes a source electrode and a p+-type region that form a metal-semiconductor junction on the n-type silicon carbide epitaxial layer, a p?-type region and another p?-type region that surround the periphery of the element structure, and an n+-type channel stopper region that surrounds the periphery of the p?-type regions so that the n-type silicon carbide epitaxial layer is therebetween. The n+-type channel stopper region has a second n+-type channel stopper region whose impurity concentration is high, and a first n+-type channel stopper region that encompasses the second n+-type channel stopper region and whose impurity concentration is lower than that of the second n+-type channel stopper region.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate insulating film, and a gate electrode. The semiconductor device further includes, in a region of the first semiconductor layer across or adjacent to a p-n junction therein that does not overlap the second semiconductor region in a plan view except lateral edges thereof, a lifetime killer region having lifetime killers implanted therein.

Abstract: In a semiconductor device, an interlayer insulating film electrically insulating a gate electrode and a source electrode has a structure in which a BPSG film and a NSG film are sequentially stacked. Further, the interlayer insulating film has a structure in which the BPSG film, the NSG film, and a SiN film are sequentially stacked, or a structure in which the BPSG film, the SiN film, and the NSG film are sequentially stacked. Such a structure enables the reliability of the semiconductor device in which a pin-shaped electrode is bonded by solder to be improved.

Abstract: Provided is a semiconductor device including a semiconductor substrate, an electrode provided on a front surface of the semiconductor substrate, where the electrode contains aluminum, a barrier layer provided between the semiconductor substrate and the electrode. Here, the barrier layer includes a first titanium nitride layer, a first titanium layer, a second titanium nitride layer and a second titanium layer in a stated order with the first titanium nitride layer being positioned closest to the semiconductor substrate.

Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type, a plurality of base regions of a second conductivity type formed on a first principal surface of the semiconductor substrate via a semiconductor layer of the first conductivity type, and a plurality of source regions of the first conductivity type formed in the base regions. Each base region, in a top-down view from an angle perpendicular to the first principle surface, is of a polygonal shape. Each adjacent two of the base regions in the top-down view have two sides, one from each of the two base regions, that face each other across a portion of the semiconductor layer, the source region being formed at only one of the two sides.

Abstract: A semiconductor device includes a silicon carbide semiconductor substrate, a first silicon carbide layer of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The third semiconductor region is thicker than the second semiconductor region and a width of a side of the third semiconductor region facing the first semiconductor region is narrower than a width of a side thereof facing the source electrode.

Abstract: Provided are a silicon carbide semiconductor device that is capable of preventing breakdown voltage degradation in the edge termination structure and a method of manufacturing the same. The p-type regions 31, 32 and the p-type region 33, which serves as an electric field relaxation region and is connected to the first p-type base regions 10, are positioned under the step-like portion 40, and the bottom surfaces of the p-type regions 31, 32, 33 are substantially flatly connected to the bottom surface of the first p-type base regions 10. The first base regions have an impurity concentration of 4×1017 cm?3 or higher. The p-type region 33 is designed to have a lower impurity concentration than the first base regions 10 and higher than the p-type regions 31, 32. In this way, the breakdown voltage degradation in the edge termination structure 102 can be prevented.