Abstract: In a side defroster device, a display device displaying an image of a vehicle exterior is provided on an instrument panel to a rear of a front pillar, and a fin provided in a defroster blower outlet is directed at an upper wall of a housing of the display device, the defroster blower outlet being provided in the front pillar and blowing out air toward a side window screen. Accordingly, air blown out from the defroster blower outlet diffuses on the upper wall of the housing, and part thereof flows toward the side window screen, thus enabling the side window screen to be demisted effectively.

Abstract: A side defroster device includes a front pillar that rises from a laterally outer end part of an instrument panel, and a defroster blower outlet that is provided in the front pillar and blows out air toward a side window screen. A display device that displays an image of a vehicle exterior is provided on the instrument panel to a rear of the front pillar. The defroster blower outlet is positioned so as to overlap, in a vehicle width direction, an upper wall of a housing when viewed in a fore-and-aft direction. Accordingly, air blown out from the defroster blower outlet diffuses on the upper wall of the housing, and part thereof flows toward the side window screen, thus enabling the side window screen to be demisted effectively.

Abstract: An interlayer insulating film covers a gate electrode and a gate insulating film embedded in a trench. A source electrode includes a first TiN film, a NiSi film, a Ti film, a second TiN film, and an Al alloy film. The first TiN film covers a part of the interlayer insulating film so as to not contact a semiconductor substrate at a bottom of a contact hole. The NiSi film forms an ohmic contact with the semiconductor substrate in the contact hole. The Ti film, the second TiN film, and the Al alloy film are sequentially stacked on surfaces of the first TiN film and the NiSi film, spanning a front surface of the semiconductor substrate, from on the interlayer insulating film. A terminal pin is soldered to the source electrode 16, in an upright position orthogonal to the front surface of the semiconductor substrate.

Abstract: In a transistor region of an active region, trench-gate MOS gates for a vertical MOSFET are formed on the front surface side of a semiconductor substrate. In a non-effective/pad region of the active region, a gate pad is formed on the front surface of the semiconductor substrate with an interlayer insulating film interposed therebetween. An n-type region is formed spanning across the entire non-effective region in the surface layer of the front surface of the semiconductor substrate. The portion directly beneath the gate pad is only an n-type region constituted by an n+ starting substrate, an n? drift region, and the n-type region, with the interlayer insulating film sandwiched thereabove. No n+ source region is formed in a p-type base region extension which is the portion of a p-type base region that extends into the non-effective region.

Abstract: A silicon carbide semiconductor device has a rectangle-shaped active region in which a main current flows, and a termination region surrounding the active region in a plan view. The device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type on the front surface of the substrate, a second semiconductor layer of a second conductivity type, at a surface at the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer, the second semiconductor region disposed from a periphery of the active region to reach the termination region, and extending along each of directions of four sides of the active region. At the four sides of the active region, a cross-sectional structure of each layer and each region of the device is identical to one another.

Abstract: In an effective region of an active region, a main semiconductor element and a source pad thereof are disposed. A non-operating region of the active region excludes the effective region and is a high-function region in which a gate pad of the main semiconductor element and other electrode pads are disposed. An edge termination region and the electrode pads are separated by an interval equivalent to at least a width of one unit cell of the main semiconductor element. In the high-function region, at a border of the edge termination region, a lead-out electrode is provided on a front surface of a semiconductor substrate. The lead-out electrode has a function of leading out displacement current that flows to the high-function region from the edge termination region when the main semiconductor element is OFF. Thus, destruction at the edge termination region may be suppressed.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type on a substrate of the first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a first semiconductor region of the first conductivity type. The semiconductor device further includes a gate electrode provided in a plurality of trenches via gate insulating films, a protruding portion disposed on the second semiconductor layer at a bridge area between two adjacent ones of the trenches in a direction orthogonal to the trenches, an interlayer insulating film provided on the gate electrode, and having contact holes that form a striped pattern, a first electrode on the interlayer insulating film and in the contact holes, a plating film provided in a plating area, and a solder on the plating film.

Abstract: A main semiconductor element and a temperature sensing part are arranged on a single silicon carbide base. The main semiconductor element is a vertical MOSFET and the temperature sensing part is a horizontal diode. An anode region of the temperature sensing part and an n+-type source region and a p+-type contact region of the main semiconductor element are connected by wiring by an anode electrode on a front surface of the silicon carbide base. The temperature sensing part, when the main semiconductor element is ON, is forward biased by drift current flowing in the main semiconductor element. The temperature sensing part, for example, is a poly-silicon diode constituted by a p-type poly-silicon layer and an n-type poly-silicon layer arranged on the front surface of the silicon carbide base. With such configuration, a semiconductor device having high reliability may be provided.

Abstract: A source pad of a main semiconductor element is electrically connected to an n+-type source region via a barrier metal. A temperature sensing part is a poly-silicon diode formed by a pn junction between a p-type poly-silicon layer that is a p-type anode region and an n-type poly-silicon layer that is an n-type cathode region. The temperature sensing part is provided, via the field insulating film, on a front surface of a same semiconductor substrate as the main semiconductor element. An anode pad and a cathode pad are in direct contact with the p-type poly-silicon layer and the n-type poly-silicon layer, respectively. The source pad, the anode pad, and the cathode pad are aluminum alloy films.

Abstract: A current sensing part that detects overcurrent of a main semiconductor element is arranged on a same silicon carbide base as the main semiconductor element. An isolating part is arranged between the main semiconductor element and the current sensing part. The isolating part has a function of suppressing interference of the main semiconductor element and the current sensing part at the silicon carbide base. The isolating part is constituted by a trench provided a predetermined depth from a front surface of the silicon carbide base. An insulating film is provided in the trench, along inner walls of the trench. A poly-silicon layer is provided on the insulating film. With such a configuration, decreases in breakdown voltage of the current sensing part may be prevented.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a first semiconductor layer, a first semiconductor region, a second semiconductor layer, a second semiconductor region, a third semiconductor region, a fourth semiconductor sub-region, a first electrode, a gate insulating film, a gate electrode, and second electrode. At a corner part of an active region in which a main current flows, a fifth semiconductor sub-region is provided. An impurity concentration of the fifth semiconductor sub-region is higher than an impurity concentration of the second semiconductor layer.

Abstract: A method of manufacturing a semiconductor device includes providing a silicon carbide (SiC) substrate, forming a SiC layer on a front surface of the SiC substrate, selectively forming a first region in the SiC layer at a surface thereof, forming a source region and a contact region in the first region, forming a gate insulating film on the SiC layer and on a portion of the first region between the SiC layer and the source region, forming a gate electrode on the gate insulating film above the portion of the first region, forming an interlayer insulating film covering the gate electrode, forming a source electrode electrically connected to the source region and the contact region, forming a drain electrode on a back surface of the SiC substrate, forming a barrier film on and covering the interlayer insulating film, and forming a metal electrode on the source electrode and the barrier film.

Abstract: A semiconductor device having a silicon carbide (SiC) substrate, a SiC layer formed on a front surface of the SiC substrate, a first region selectively formed in the SiC layer at a surface thereof, a source region and a contact region formed in the first region, a gate insulating film disposed on the SiC layer and on a portion of the first region between the SiC layer and the source region, a gate electrode disposed on the gate insulating film above the portion of the first region, an interlayer insulating film covering the gate electrode, a source electrode electrically connected to the source region and the contact region, a drain electrode formed on a back surface of the SiC substrate, a first barrier film formed on, and covering, the interlayer insulating film, and a metal electrode formed on the source electrode and the first barrier film.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate insulating film, and a gate electrode. The semiconductor device further includes, in a region of the first semiconductor layer across or adjacent to a p-n junction therein that does not overlap the second semiconductor region in a plan view except lateral edges thereof, a lifetime killer region having lifetime killers implanted therein.

Abstract: A semiconductor device includes a silicon carbide semiconductor substrate, a first silicon carbide layer of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The third semiconductor region is thicker than the second semiconductor region and a width of a side of the third semiconductor region facing the first semiconductor region is narrower than a width of a side thereof facing the source electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate electrode, a first electrode, and a gate electrode pad. A first lower region opposing the gate electrode pad in a depth direction has a carrier recombination rate that is lower than that of a second lower region opposing the first electrode in the depth direction. With such a configuration, when high electric potential is applied to a source electrode and a built-in PN diode is driven, the generation of crystal defects may be suppressed.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the first conductivity type, a gate insulating film, and a gate electrode. A threshold voltage of the semiconductor device is higher than forward voltage of a built-in PN diode constituted by the second semiconductor layer, the semiconductor substrate, and the first semiconductor layer. Thus, when high electric potential is applied to a source electrode and the built-in PN diode is driven, the generation of crystal effects may be suppressed.

Abstract: On a front surface of an n+-type SiC substrate becoming a drain region, an n?-type drift layer, a p-type base layer, and an n+-type source layer are sequentially formed by epitaxial growth. In the n+-type source layer, the p+-type contact region is selectively provided. A trench is provided penetrating the n+-type source layer and the p-type base layer in the depth direction and reaching the n?-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 ?m or less. A depth of the trench is, for example, 1 ?m or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented.

Abstract: An interlayer insulating film covers a gate electrode and a gate insulating film embedded in a trench. A source electrode includes a first TiN film, a NiSi film, a Ti film, a second TiN film, and an Al alloy film. The first TiN film covers a part of the interlayer insulating film so as to not contact a semiconductor substrate at a bottom of a contact hole. The NiSi film forms an ohmic contact with the semiconductor substrate in the contact hole. The Ti film, the second TiN film, and the Al alloy film are sequentially stacked on surfaces of the first TiN film and the NiSi film, spanning a front surface of the semiconductor substrate, from on the interlayer insulating film. A terminal pin is soldered to the source electrode 16, in an upright position orthogonal to the front surface of the semiconductor substrate.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type provided on a front surface of a semiconductor substrate of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; and a gate electrode having a striped-shape and provided on a gate insulating film. The silicon carbide semiconductor device further includes a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region; a step film provided on the first electrode; a plating film provided on the first electrode and the step film; and a solder on the plating film. The step film is provided on the first electrode on which the solder and the plating film are provided, the step film being provided so as to be embedded in grooves formed on the first electrode.