Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Abstract: Provided is a device including a fin structure and methods for forming such a device. A method includes forming an initial fin having a sidewall. Further, the method includes forming an additional layer of fin material over the sidewall, wherein the additional layer has a thickness. Also, the method includes adjusting the thickness of the additional layer of fin material to form a fin structure with a desired critical dimension.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first t

Abstract: In an embodiment, a device includes: a first semiconductor strip over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip.

Abstract: A method of manufacturing a semiconductor device includes forming a dummy gate structure over a substrate. The dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode layer. Sidewall spacers including one or more layers of insulating materials are formed on sidewalls of the dummy gate structure. A silicon based liner is formed over the sidewall spacers. A first insulating layer is formed over the silicon based liner. The silicon based liner and the first insulating layer are thermally treating causing a reduction in a volume of the first insulating layer and an increase in a volume of the silicon based liner. The dummy gate structure is removed to form a gate space in the first insulating layer. The gate space is formed with a high-k dielectric layer and a first conductive layer.

Abstract: A semiconductor device includes a plurality of nanostructures, a gate dielectric layer disposed on each nanostructure of the plurality of nanostructures, a gate electrode disposed on the gate dielectric layer and on the plurality of nanostructures, and a source/drain region adjacent to the nanostructures. The source/drain region includes an epitaxial structure including a polygonal-shaped upper portion and a column-like lower portion, wherein the polygonal-shaped upper portion has multiple facets, and each of the facets characterized by a (111) crystallographic orientation. The polygonal-shaped upper portion includes corner regions adjacent an intersection of two facets with a (111) crystallographic orientation and an epitaxial body region in contact with the corner regions. The corner regions are characterized by a first dopant concentration and the epitaxial body region is characterized by a second dopant concentration, and the first dopant concentration is higher than the second dopant concentration.

Abstract: A system and methods of manufacturing semiconductor devices is described herein. The method includes forming a recess between fins in a substrate and forming a dielectric layer over the fins and in the recess. Once the dielectric layer has been formed, a bottom seed structure is formed over the dielectric layer within the recess and the dielectric layer is exposed along sidewalls of the recess. A dummy gate material is grown from the bottom seed structure in a bottom-up deposition process without growing the dummy gate material from the dielectric layer exposed along sidewalls of the recess.

Abstract: A method for manufacturing a semiconductor device includes: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; and subjecting the patterned structure to an ion implantation process so as to modulate a profile of the dummy gate structure.

Abstract: In an embodiment, an apparatus includes a first pyrometer and a second pyrometer configured to monitor thermal radiation from a first point and a second point on a backside of a wafer, respectively, a first heating source in a first region and a second heating source in a second region of an epitaxial growth chamber, respectively, where a first controller adjusts an output of the first heating source and the second heating source based upon the monitored thermal radiation from the first point and the second point, respectively, a third pyrometer and a fourth pyrometer configured to monitor thermal radiation from a third point and a fourth point on a frontside of the wafer, respectively, where a second controller adjusts a flow rate of one or more precursors injected into the epitaxial growth chamber based upon the monitored thermal radiation from the first, second, third, and fourth points.

Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.

Abstract: An intensity of a power laser beam applied to a semiconductor device is adjusted. An applied intensity of the power laser beam is indicative of a magnitude at which the power laser beam is emitted toward the semiconductor device and a reflection intensity of a probing laser beam applied to the semiconductor device is indicative of an emissivity of the semiconductor device. The reflection intensity of the probing laser beam is measured to determine the emissivity of the semiconductor device and the applied intensity of the power laser beam is adjusted as a function of the emissivity.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.

Abstract: In an embodiment, a device includes: a first semiconductor strip over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip.

Abstract: Embodiments of an ion cryo-implantation process utilize a post implantation heating stage to heat the implanted wafer while under the heavy vacuum used during cryo-implantation. The implanted wafer is then transferred to load locks which are held at a lesser vacuum than the heavy vacuum.

Abstract: A method of forming a semiconductor device includes removing a light-sensitive material from a workpiece utilizing polarized electromagnetic radiation and annealing features on the workpiece utilizing electromagnetic radiation polarized in a different direction than the polarized electromagnetic radiation utilized to remove the light-sensitive material. In some embodiments, the electromagnetic radiation used to anneal the features on the workpiece is not polarized. In some described embodiments, light-sensitive material removed from the workpiece is exhausted from the chamber in which the light-sensitive removal process is carried out before it can deposit on surfaces of the chamber.

Abstract: In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.

Abstract: In an embodiment, a method of forming a semiconductor device includes: forming a first oxide layer over a semiconductor fin structure; performing a first nitridation process to convert the first oxide layer to an oxynitride layer; depositing a silicon-containing layer over the oxynitride layer; performing a first anneal on the silicon-containing layer, wherein after performing the first anneal, the oxynitride layer has a higher nitrogen atomic concentration at an interface with the semiconductor fin structure than in a bulk region of the oxynitride layer; and forming a dummy gate structure over the silicon-containing layer.

Abstract: An annealing apparatus includes: a first chamber including a first gas having a first gas pressure; a second chamber configured to receive a second gas having a second gas pressure; gas inlets; gas vents; heating elements laterally surrounding the first chamber; and a controller configured to perform the steps of: heating the first chamber while keeping a gas pressure difference between the first gas pressure and the second gas pressure is within a tolerance limit; and cooling the first chamber by exchanging the second gas in the second chamber while keeping the gas pressure difference within the tolerance limit, wherein the exchanging of the second gas includes introducing the second gas to the second chamber through the plurality of gas inlets and exhausting a the second gas out of the second chamber through the plurality of gas vents while keeping the second gas pressure unchanged.