Abstract: A method includes forming a gate structure over fins protruding from a semiconductor substrate; forming an isolation region surrounding the fins; depositing a spacer layer over the gate structure and over the fins, wherein the spacer layer fills the regions extending between pairs of adjacent fins; performing a first etch on the spacer layer, wherein after performing the first etch, first remaining portions of the spacer layer that are within inner regions extending between pairs of adjacent fins have a first thickness and second remaining portions of the spacer layer that are not within the inner regions have a second thickness less than the first thickness; and forming an epitaxial source/drain region adjacent the gate structure and extending over the fins, wherein portions of the epitaxial source/drain region within the inner regions are separated from the first remaining portions of the spacer layer.

Abstract: A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.

Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a source/drain feature over a substrate, a plurality of semiconductor layers over the substrate, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a gate dielectric layer in contact with the gate electrode layer, and a cap layer. The cap layer has a first portion disposed between the plurality of semiconductor layers and the source/drain feature and a second portion extending outwardly from opposing ends of the first portion. The semiconductor device structure further includes a dielectric spacer disposed between and in contact with the source/drain feature and the second portion of the cap layer.

Abstract: A method includes forming a gate structure over fins protruding from a semiconductor substrate; forming an isolation region surrounding the fins; depositing a spacer layer over the gate structure and over the fins, wherein the spacer layer fills the regions extending between pairs of adjacent fins; performing a first etch on the spacer layer, wherein after performing the first etch, first remaining portions of the spacer layer that are within inner regions extending between pairs of adjacent fins have a first thickness and second remaining portions of the spacer layer that are not within the inner regions have a second thickness less than the first thickness; and forming an epitaxial source/drain region adjacent the gate structure and extending over the fins, wherein portions of the epitaxial source/drain region within the inner regions are separated from the first remaining portions of the spacer layer.

Abstract: A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.

Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

Abstract: Provided is an epitaxial structure and a method for forming such a structure. The method includes forming a fin structure on a substrate, wherein the fin structure includes a semiconductor material having substantially a {110} crystallographic orientation. The method includes etching a portion of the fin structure to expose a sidewall portion of the semiconductor material. Further, the method includes growing an epitaxial structure on the sidewall of the semiconductor material, wherein the epitaxial structure propagates with facets having a {110} crystallographic orientation.

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

Abstract: A method is disclosed that includes performing a directional ion implantation process on a developed resist pattern to reduce roughness. A substrate can be tilted at a tilt angle with respect to the direction of an incoming ion beam. Ions can be directionally implanted at the tilt angle, along sidewall surfaces of the developed resist pattern to trim roughness from the sidewall surfaces. After implanting, the substrate can be rotated along the axis normal to a surface, and ions can then be directionally implanted at the tilt angle along the sidewall surfaces to further trim roughness from the sidewall surfaces of the developed resist pattern. The directional ion implantation process can be performed over a number of iterations, and during each iteration of the directional ion implantation process, the tilt angle can be adjusted so that the tilt angle is different than during previous iterations.

Abstract: A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.

Abstract: A method includes forming a semiconductor fin protruding over a substrate; forming an isolation structure over the substrate; depositing a first metal oxide layer over the isolation structure; depositing a first oxide layer over the first metal oxide layer; depositing a second metal oxide layer over the first oxide layer, in which the first metal oxide layer and the second metal oxide layer comprise amorphous structures; performing a chemical mechanism polishing (CMP) process to the first metal oxide layer, the first oxide layer, and the second metal oxide layer; after the CMP process is completed, performing an annealing process such that the first metal oxide layer and the second metal oxide layer are transferred from the amorphous structures into crystalline structures; forming a gate structure over the semiconductor fin; and forming source/drain structures over the substrate and on opposite sides of the gate structure.

Abstract: A method includes forming a plurality of channel layers above a (110)-orientated substrate, the channel layers arranged in a <110> direction normal to a top surface the (110)-orientated substrate and extending in a <110> direction perpendicular to the <110> direction; epitaxial growing a plurality of silicon layers on either side of each of the channel layers; doping the silicon layers with boron; epitaxial growing a plurality of first silicon germanium layers on the silicon layers; forming a gate structure surrounding each of the channel layers.

Abstract: A device includes a first nanostructure over a substrate and a first source/drain region adjacent the first nanostructure. The first source/drain region includes a first epitaxial layer covering a first sidewall of the first nanostructure. The first epitaxial layer has a first concentration of a first dopant. The first epitaxial layer has a round convex profile opposite the first sidewall of the first nanostructure in a cross-sectional view. The first source/drain region further includes a second epitaxial layer covering the round convex profile of the first epitaxial layer in the cross-sectional view. The second epitaxial layer has a second concentration of the first dopant, the second concentration being different from the first concentration.

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Abstract: In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

Abstract: A method of forming a semiconductor device includes forming a sacrificial gate structure over a substrate, depositing a spacer layer on the sacrificial gate structure in a conformal manner, performing a multi-step oxidation process to the spacer layer, etching the spacer layer to form gate sidewall spacers on opposite sidewalls of the sacrificial gate structure, removing the sacrificial gate structure to form a trench between the gate sidewalls spacers, and forming a metal gate structure in the trench.

Abstract: The present disclosure is directed to methods for forming source/drain (S/D) epitaxial structures with a hexagonal shape. The method includes forming a fin structure that includes a first portion and a second portion proximate to the first portion, forming a gate structure on the first portion of the fin structure, and recessing the second portion of the fin structure. The method further includes growing a S/D epitaxial structure on the recessed second portion of the fin structure, where growing the S/D epitaxial structure includes exposing the recessed second portion of the fin structure to a precursor and one or more reactant gases to form a portion of the S/D epitaxial structure. Growing the S/D epitaxial structure further includes exposing the portion of the S/D structure to an etching chemistry and exposing the portion of the S/D epitaxial structure to a hydrogen treatment to enhance growth of the S/D epitaxial structure.

Abstract: A semiconductor structure includes a substrate and a stacked structure including channel layers interleaved with a metal gate structure. The semiconductor structure also includes an isolation feature disposed between the stacked structure and the substrate, where a bottommost portion of the metal gate structure directly contacts the isolation feature. The semiconductor structure further includes a source/drain feature disposed adjacent the stacked structure and an inner spacer disposed between the metal gate structure and the source/drain feature.

Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.