Patents by Inventor Yen-An Chang

Yen-An Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961629
    Abstract: An antioxidant conductive thermal paste and a method of manufacturing the same are provided. The antioxidant conductive thermal paste includes a reactive monomer, a thermosetting resin, a polymerization inhibitor, an electrically conductive filler, and a thixotropic agent. The method consists of the steps of mixing a reactive monomer, a thermosetting resin, and a polymerization inhibitor evenly to get a first polymer mixture, and adding an electrically conductive filler and a thixotropic agent into the first polymer mixture in turn and blending the mixture evenly to obtain an antioxidant conductive thermal paste with good adherence, high electrical conductivity, high thermal conductivity, improved thermal-mechanical fatigue resistance or mechanical fatigue resistance.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: April 16, 2024
    Assignee: Geckos Technology Corp.
    Inventors: Wei-Chen Chang, Chen-Yen Fan, Ping-Hung Chen, Tsung-Huan Sheng
  • Publication number: 20240120430
    Abstract: A method of forming infrared detector includes the following operations. A sensing structure including a first infrared absorption layer, a first protection layer, a second infrared absorption layer, and a second protection layer from bottom to top is received. A patterned photoresist layer is formed on the sensing structure, in which the patterned photoresist layer has a first opening exposing the second protection layer. The second protection layer is etched through the first opening to form a second opening in the second protection layer, in which the second opening exposes the second infrared absorption layer. The patterned photoresist layer is removed. The second infrared absorption layer and the first protection layer are etched through the second opening to form a third opening, in which the third opening exposes the first infrared absorption layer. An electrode is formed in the third opening.
    Type: Application
    Filed: February 16, 2023
    Publication date: April 11, 2024
    Inventor: Yen-Chang CHEN
  • Publication number: 20240120282
    Abstract: The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.
    Type: Application
    Filed: February 20, 2023
    Publication date: April 11, 2024
    Inventors: TZU-WEI CHIU, CHUN-WEI CHANG, SHANG-PIN CHEN, WEI-CHIH CHEN, CHE-YEN HUANG
  • Patent number: 11955441
    Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Publication number: 20240112707
    Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 4, 2024
    Applicant: Etron Technology, Inc
    Inventors: Der-Min Yuan, Yen-An Chang, Wei-Ming Huang
  • Publication number: 20240113071
    Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
  • Publication number: 20240112870
    Abstract: A backlight module for a lighting keyboard comprises a lighting board including light emitting units, a light guide panel disposed on the lighting board and including light guide holes, and a shielding sheet disposed on the light guide panel. Each light emitting unit is located in each light guide hole. The backlight module is divided into regions including a middle region and two first side regions located outside the middle region. The light guide holes include at least one middle light guide hole in the middle region and at least one first light guide hole in the first side region. A distance between a light emitting unit located in the middle light guide hole and a wall of the middle light guide hole is lesser than a distance between a light emitting unit located in the first light guide hole and a wall of the first light guide hole.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 4, 2024
    Applicant: Darfon Electronics Corp.
    Inventors: Yen-Chang CHEN, Heng-Yi HUANG
  • Patent number: 11944412
    Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Ying-Lun Chang, Ching-Sung Lin, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee, Chun-Yi Kuo, Tsung-I Lin
  • Patent number: 11944960
    Abstract: The present disclosure provides a method for fabricating a nickel-cerium dioxide-aluminum oxide hybrid nanoparticle cluster catalyst. The method includes a solution preparation step, an aerosolizing step, a drying step, a first calcining step, a reducing gas adding step, and a second calcining step. The solution preparation step is provided for preparing a precursor solution. The aerosolizing step is performed for obtaining an atomized droplet. The drying step is performed for converting to a precursor crystallite. The first calcining step is performed for obtaining an oxidation state catalyst. The reducing gas adding step is performed for adding hydrogen. The second calcining step is performed for obtaining the nickel-cerium dioxide-aluminum oxide hybrid nanoparticle cluster catalyst.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: April 2, 2024
    Assignees: NATIONAL TSING HUA UNIVERSITY, Chang Chun Plastics Co., Ltd., Chang Chun Petrochemical Co., LTD., DAIREN CHEMICAL CORP.
    Inventors: De-Hao Tsai, Hung-Yen Chang, Guan-Hung Lai
  • Patent number: 11948926
    Abstract: In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Chieh-Yen Chen
  • Publication number: 20240104309
    Abstract: A method includes receiving an input for a large language model (LLM) from a user. The method also includes generating one or more token embeddings based on the input. The method further includes generating one or more prompt embeddings based on the input using a contextual prompt generator (CPG), the one or more prompt embeddings representing new or updated information that is not contained in existing knowledge of the LLM. The method also includes providing the one or more token embeddings and the one or more prompt embeddings to the LLM. In addition, the method includes outputting a prediction based on the one or more token embeddings and the one or more prompt embeddings using the LLM, wherein the prediction reflects the new or updated information represented by the one or more prompt embeddings.
    Type: Application
    Filed: September 12, 2023
    Publication date: March 28, 2024
    Inventors: Yen-Chang Hsu, Harshavardhan Kamarthi, Yilin Shen, Hongxia Jin
  • Publication number: 20240105779
    Abstract: A method includes performing a first deposition process to form a first graphene layer over a substrate, the first deposition process being performed under a first temperature and a first pressure; performing a second deposition process to form a second graphene layer over the first graphene layer, the second deposition process being performed under a second temperature and a second pressure, in which the first temperature is higher than the second temperature, and the first pressure is lower than the second pressure; forming a gate structure over the second graphene layer; and forming source/drain contacts on opposite sides of the gate structure and electrically connected to the first and second graphene layers.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 28, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yen LIN, Che-Jia CHANG
  • Patent number: 11942451
    Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Yu-Chia Lai, Cheng-Shiuan Wong, Ting Hao Kuo, Ching-Hua Hsieh, Hao-Yi Tsai, Kuo-Lung Pan, Hsiu-Jen Lin
  • Patent number: 11937574
    Abstract: An interactive device for animals is provided that includes a main body, a driving module and a first rotating member. The main body includes an accommodating groove, an opening, and a communicating channel. The driving module is disposed on the main body. The first rotating member is rotatably disposed in the main body and separates the communicating channel and the accommodating groove. When the driving module drives the first rotating member to rotate in a first rotating direction, the first rotating member drives at least one object disposed in the accommodating groove to enter the communicating channel and leave the main body through the opening.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: March 26, 2024
    Assignee: TOMOFUN CO., LTD.
    Inventors: Chia-Yen Chang, Min-Wei Chen, Yo-Chen Victor Chang
  • Patent number: 11939431
    Abstract: The present invention relates to a composition comprising an amino acid-modified polymer, a carboxypolysaccharide, and may further include a metal ion for anti-adhesion and vector application. More specifically, the invention relates to a thermosensitive composition having enhanced mechanical and improved water-erosion resistant properties for efficiently preventing tissue adhesions and can serve as a vector with bio-compatible, bio-degradable/absorbable, and in-vivo sustainable properties.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 26, 2024
    Assignee: PROVIEW-MBD BIOTECH CO., LTD.
    Inventors: Yu-Chia Chang, Yunn-Kuen Chang, Wen-Yen Huang, Ging-Ho Hsiue, Hsieh-Chih Tsai, Shuian-Yin Lin, Nai-Sheng Hsu, Tzu-Yu Lin
  • Patent number: 11939432
    Abstract: Synthetic amino acid-modified polymers and methods of making the same and using the same are disclosed. The synthetic amino acid-modified polymers possess distinct thermosensitive, improved water-erosion resistant, and enhanced mechanical properties, and are suitable of reducing or preventing formation of postoperative tissue adhesions. Additionally, the amino acid-modified polymers can also be used as a vector to deliver pharmaceutically active agents.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 26, 2024
    Assignee: PROVIEW-MBD BIOTECH CO., LTD.
    Inventors: Yu-Chia Chang, Yunn-Kuen Chang, Wen-Yen Huang, Ging-Ho Hsiue, Hsieh-Chih Tsai, Shuian-Yin Lin, Nai-Sheng Hsu, Tzu-Yu Lin
  • Publication number: 20240096928
    Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate and a metallization structure over the substrate. The metallization structure includes a MIM structure, a first contact and a second contact. The MIM structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, and a top electrode layer on the ferroelectric layer. The ferroelectric layer is substantially made of lead zirconate titanate (PZT), BaTiO3 (BTO), or barium strontium titanate (BST), and a thickness of the ferroelectric layer is greater than a thickness of the dielectric layer.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Inventors: SAI-HOOI YEONG, CHIH-YU CHANG, CHUN-YEN PENG, CHI ON CHUI
  • Publication number: 20240088023
    Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Shao-Kuan LEE, Kuang-Wei YANG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
  • Patent number: 11929401
    Abstract: Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Wei Lee, Hsueh-Chang Sung, Yen-Ru Lee
  • Publication number: 20240078342
    Abstract: Examples described herein relate to a security management system to secure a container ecosystem. In some examples, the security management system may protect one or more entities such as container management applications, container images, containers, and/or executable applications within the containers. The security management system may make use of digital cryptography to generate digital signatures corresponding to one or more of these entities and verify them during the execution so that any compromised entities can be blocked from execution and the container ecosystem may be safeguarded from any malicious network attacks.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 7, 2024
    Inventors: Wan-Yen Hsu, Chih-Hao Chang, Lin-Chan Hsiao