Patents by Inventor Yen-An SHIH
Yen-An SHIH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10109559Abstract: An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part.Type: GrantFiled: August 27, 2014Date of Patent: October 23, 2018Assignee: XINTEC INC.Inventors: Chia-Sheng Lin, Yen-Shih Ho, Tsang-Yu Liu
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Patent number: 10096635Abstract: A semiconductor structure includes a chip, a light transmissive plate, a spacer, and a light-shielding layer. The chip has an image sensor, a first surface and a second surface opposite to the first surface. The image sensor is located on the first surface. The light transmissive plate is disposed on the first surface and covers the image sensor. The spacer is between the light transmissive plate and the first surface, and surrounds the image sensor. The light-shielding layer is located on the first surface between the spacer and the image sensor.Type: GrantFiled: August 5, 2015Date of Patent: October 9, 2018Assignee: XINTEC INC.Inventors: Wei-Ming Chien, Po-Han Lee, Tsang-Yu Liu, Yen-Shih Ho
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Patent number: 10049252Abstract: A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.Type: GrantFiled: December 11, 2015Date of Patent: August 14, 2018Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Shu-Ming Chang, Tsang-Yu Liu, Hsing-Lung Shen
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Patent number: 10050006Abstract: A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.Type: GrantFiled: April 10, 2017Date of Patent: August 14, 2018Assignee: XINTEC INC.Inventors: Chia-Lun Shen, Yi-Ming Chang, Tsang-Yu Liu, Yen-Shih Ho
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Publication number: 20180175101Abstract: A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer. A second surface of the wafer facing away from the first carrier is etched to form at least one through hole and at least one trench, in which a conductive pad of the wafer is exposed through the through hole. An isolation layer is formed on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench. A second carrier is adhered to the second surface of the wafer by a second temporary bonding layer, and thus the through hole and the trench are covered by the second carrier. The first carrier and the first temporary bonding layer are removed.Type: ApplicationFiled: December 20, 2017Publication date: June 21, 2018Inventors: Yen-Shih Ho, Tsang-Yu Liu, Chia-Sheng Lin, Chaung-Lin Lai
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Patent number: 9997473Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.Type: GrantFiled: January 18, 2017Date of Patent: June 12, 2018Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Tsang-Yu Liu, Chia-Sheng Lin, Chaung-Lin Lai
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Patent number: 9978788Abstract: A method for forming a photosensitive module is provided. The method includes providing a sensing device. The sensing device includes a conducting pad located on a substrate. A first opening penetrates the substrate and exposes the conducting pad. A redistribution layer is in the first opening to electrically connect to the conducting pad. A cover plate is located on the substrate and covers the conducting pad. The method also includes removing the cover plate of the sensing device. The method further includes bonding the sensing device to a circuit board after the removal of the cover plate. The redistribution layer in the first opening is exposed and faces the circuit board. In addition, the method includes mounting an optical component corresponding to the sensing device on the circuit board. A photosensitive module formed by the method is also provided.Type: GrantFiled: January 25, 2016Date of Patent: May 22, 2018Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Tsang-Yu Liu, Chi-Chang Liao
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Patent number: 9947716Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 ?m to 750 ?m, and the wall surface of the dam element surrounding the sensing area is a rough surface.Type: GrantFiled: November 22, 2016Date of Patent: April 17, 2018Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Hsiao-Lan Yeh, Chia-Sheng Lin, Yi-Ming Chang, Po-Han Lee, Hui-Hsien Wu, Jyun-Liang Wu, Shu-Ming Chang, Yu-Lung Huang, Chien-Min Lin
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Publication number: 20180102321Abstract: A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.Type: ApplicationFiled: October 3, 2017Publication date: April 12, 2018Inventors: Yen-Shih HO, Po-Han LEE, Chia-Ming CHENG, Hsin-Yen LIN
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Patent number: 9887229Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a firstType: GrantFiled: August 2, 2016Date of Patent: February 6, 2018Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Tsang-Yu Liu, Chia-Sheng Lin, Chia-Ming Cheng
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Patent number: 9881889Abstract: A chip package is provided, in which includes: a packaging substrate, a chip and a plurality solder balls interposed between the packaging substrate and the chip for bonding the packaging substrate and the chip, wherein the solder balls include a first portion of a first size and a second portion of a second size that is different from the first size.Type: GrantFiled: April 11, 2014Date of Patent: January 30, 2018Assignee: XINTEC INC.Inventors: Yu-Lung Huang, Shu-Ming Chang, Tsang-Yu Liu, Yen-Shih Ho
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Patent number: 9875912Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.Type: GrantFiled: November 21, 2016Date of Patent: January 23, 2018Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Hsiao-Lan Yeh, Chia-Sheng Lin, Yi-Ming Chang, Po-Han Lee, Hui-Hsien Wu, Jyun-Liang Wu
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Patent number: 9842891Abstract: A pixel circuit is provided comprising the following. The first transistor includes a gate electrode and a semiconductor layer comprising a channel region, a source region, a first drain region, and a second drain region. A first portion of the channel region is connected to the source region, a second portion of the channel region is connected to the first drain region, and a third portion of the channel region is connected to the second drain region. The channel width of the second portion is greater than that of the third portion. A capacitive device is connected to the gate of the first transistor. The second transistor includes a source region connected to the second drain region and a drain region connected to the light-emitting element. The third transistor includes a source region connected to the first drain region and a drain region connected to a capacitive device.Type: GrantFiled: July 28, 2017Date of Patent: December 12, 2017Assignee: AU OPTRONICS CORPORATIONInventors: Chi-Yu Yeh, Chen-Ming Hu, Yen-Shih Huang
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Publication number: 20170332014Abstract: The present invention provides a method for transforming a wide-angle image to a map projection image that includes the steps of: capturing a wide-angle image; choosing an azimuthal coordinate model and introducing the wide-angle image into the chosen azimuthal coordinate model to obtain an azimuthal image; and generating a compensation image by using the azimuthal image to generate the map projection image. The present invention also provides a method for transforming a wide-angle image to a perspective projection image that includes the same steps. The present invention facilitates generation of virtual reality images.Type: ApplicationFiled: May 12, 2017Publication date: November 16, 2017Inventor: Kuang-Yen Shih
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Publication number: 20170323933Abstract: A pixel circuit is provided comprising the following. The first transistor includes a gate electrode and a semiconductor layer comprising a channel region, a source region, a first drain region, and a second drain region. A first portion of the channel region is connected to the source region, a second portion of the channel region is connected to the first drain region, and a third portion of the channel region is connected to the second drain region. The channel width of the second portion is greater than that of the third portion. A capacitive device is connected to the gate of the first transistor. The second transistor includes a source region connected to the second drain region and a drain region connected to the light-emitting element. The third transistor includes a source region connected to the first drain region and a drain region connected to a capacitive device.Type: ApplicationFiled: July 28, 2017Publication date: November 9, 2017Inventors: Chi-Yu YEH, Chen-Ming HU, Yen-Shih HUANG
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Patent number: 9793234Abstract: A chip package includes a first chip and a second chip. The first chip includes a first substrate having a first surface and a second surface opposite to the first surface, a first passive element on the first surface, and a first protection layer covering the first passive element, which the first protection layer has a third surface opposite to the first surface. First and second conductive pad structures are disposed in the first protection layer and electrically connected to the first passive element. The second chip is disposed on the third surface, which the second chip includes an active element and a second passive element electrically connected to the active element. The active element is electrically connected to the first conductive pad structure.Type: GrantFiled: April 5, 2016Date of Patent: October 17, 2017Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Shu-Ming Chang, Hsing-Lung Shen
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Patent number: 9780251Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.Type: GrantFiled: March 6, 2017Date of Patent: October 3, 2017Assignee: XINTEC INC.Inventors: Wei-Luen Suen, Wei-Ming Chien, Po-Han Lee, Tsang-Yu Liu, Yen-Shih Ho
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Publication number: 20170271276Abstract: A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.Type: ApplicationFiled: March 16, 2017Publication date: September 21, 2017Inventors: Yen-Shih HO, Chia-Sheng LIN, Po-Han LEE, Wei-Luen SUEN
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Patent number: 9761555Abstract: A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.Type: GrantFiled: January 23, 2015Date of Patent: September 12, 2017Assignee: XINTEC INC.Inventors: Jiun-Yen Lai, Yu-Wen Hu, Bai-Yao Lou, Chia-Sheng Lin, Yen-Shih Ho, Hsin Kuan
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Patent number: 9755007Abstract: A pixel circuit is provided comprising the following. The first transistor includes a gate electrode and a semiconductor layer comprising a channel region, a source region, a first drain region, and a second drain region. A first portion of the channel region is connected to the source region, a second portion of the channel region is connected to the first drain region, and a third portion of the channel region is connected to the second drain region. The channel width of the second portion is greater than that of the third portion. A capacitive device is connected to the gate of the first transistor. The second transistor includes a source region connected to the second drain region and a drain region connected to the light-emitting element. The third transistor includes a source region connected to the first drain region and a drain region connected to a capacitive device.Type: GrantFiled: June 14, 2016Date of Patent: September 5, 2017Assignee: AU OPTRONICS CORPORATIONInventors: Chi-Yu Yeh, Chen-Ming Hu, Yen-Shih Huang