Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first

Abstract: A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.

Abstract: A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.

Abstract: This invention provides a touch panel-sensing chip package module complex, comprising: a touch panel with a first top surface and a first bottom surface opposite to each other, wherein the first bottom surface having a first cavity with a bottom wall surrounded by a sidewall; a color layer formed on the bottom wall and the first bottom surface adjacent to the cavity; and a chip scale sensing chip package module bonded to the cavity by the color layer formed on the bottom wall of the cavity.

Abstract: A semiconductor structure includes a first substrate, a second substrate, a dam layer, a photoresist layer, and a conductive layer. The first substrate has a conductive pad. The second substrate has a through via, a sidewall surface surrounding the through via, a first surface, and a second surface opposite to the first surface. The through via penetrates through the first and second surfaces. The conductive pad is aligned with the through via. The dam layer is located between the first substrate and the second surface. The dam layer protrudes toward the through via. The photoresist layer is located on the first surface, the sidewall surface, the dam layer protruding toward the through via, and between the conductive pad and the dam layer protruding toward the through via. The conductive layer is located on the photoresist layer and the conductive pad.

Abstract: A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.

Abstract: A semiconductor electroplating system includes a conducting ring and at least one conductive device. The conducting ring is used for carrying a wafer. The conducting ring has at least two connecting points. The wafer has a first surface and an opposite second surface. An isolation layer is located on the second surface. Two ends of the conductive device are respectively connected to the two connecting points of the conducting ring. When the conducting ring is immersed in the plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer. The conductive device is used for transmitting a partial current that passes through one of the connecting points to the other connecting point.

Abstract: A chip package includes a first chip and a second chip. The first chip includes a first substrate having a first surface and a second surface opposite to the first surface, a first passive element on the first surface, and a first protection layer covering the first passive element, which the first protection layer has a third surface opposite to the first surface. First and second conductive pad structures are disposed in the first protection layer and electrically connected to the first passive element. The second chip is disposed on the third surface, which the second chip includes an active element and a second passive element electrically connected to the active element. The active element is electrically connected to the first conductive pad structure.

Abstract: A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.

Abstract: This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to the first top surface, which comprises a sensing device near the first top surface, a plurality of conductive pads near the first top surface and adjacent to the sensing device; a plurality of through holes on the first top surface and each of the through holes exposing one of the conductive pads corresponding to with each other; a plurality of conductive structure formed on the first bottom surface; and a re-distribution layer (RDL) formed on the first bottom surface and the first through holes to respectively connect to each of the conductive pads and each of the conductive structures; a spacing layer, surrounding the sensing chip, formed on the sensing chip.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

Abstract: This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to each other, a touch plate having a second top surface and a second bottom surface opposite to each other, formed above the sensing chip, and a color layer, sandwiched between the sensing chip and the touch plate, wherein the sensing chip comprises a sensing device formed nearby the first top surface and a plurality of conductive pads formed nearby the first top surface and adjacent to the sensing device, a plurality of through silicon vias exposing their corresponding conductive pads formed on the first bottom surface, a plurality of conductive structures formed on the first bottom surface, and a re-distribution layer overlaying the first bottom surface and each through silicon via to electrically connect each conductive pad and each conductive structure.

Abstract: A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.

Abstract: A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.

Abstract: An embodiment of this invention provides a chip scale sensing chip package module, comprising a chip scale sensing chip package, having a sensing chip with a first top substrate and a first bottom substrate opposite to the first top substrate, wherein the sensing chip has a sensing device and a plurality of conductive pads adjacent to the first top substrate, and a plurality of conductive structures connected to the conductive pads by a re-distribution layer adjacent to the first bottom surface; a touch plate having a color layer, comprising a base and a spacer formed on the base, wherein the spacer has a cavity with a bottom wall exposing part of the surface of the base and a side wall surrounding the bottom wall; and a first adhesive layer sandwich between the sensing chip and the touch plate to join the first top surface of the sensing chip to the bottom wall of the cavity of the touch plate and surround the sensing chip by the side wall of the cavity; and a print circuit board placed under the chip scale

Abstract: A chip package includes a chip, a dielectric bonding layer, a carrier, and a redistribution layer. The chip has a substrate, a conductive pad, and a protection layer. The dielectric bonding layer is located on the protection layer and between the carrier and the protection layer. The carrier, the dielectric bonding layer, and the protection layer have a communicated through hole configured to expose the conductive pad. The redistribution layer includes a connection portion and a passive component portion. The connection portion is located on the conductive pad, the sidewall of the through hole, and a surface of the carrier facing away from the dielectric bonding layer. The passive component portion is located on the surface of the carrier, and an end of the passive component portion is connected to the connection portion that is on the surface of the carrier.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A second surface of the wafer is adhered to an ultraviolet tape on a frame, and the temporary bonding layer and the carrier are removed. A protection tape is adhered to the first surface of the wafer. An ultraviolet light is used to irradiate the ultraviolet tape. A dicing tape is adhered to the protection tape and the frame, and the ultraviolet tape is removed. A first cutter is used to dice the wafer from the second surface of the wafer, such that plural chips and plural gaps between the chips are formed. A second cutter with a width smaller than the width of the first cutter is used to cut the protection tape along the gaps.

Abstract: A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The semiconductor chip has a first conducting pad disposed on a lower surface, and a first hole corresponding to the first conducting pad. The first hole and the isolation layer extend from an upper surface to the lower surface to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has a redistributing metal line corresponding to the first conducting pad, the redistributing metal line is connected to the first conducting pad through the opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the first conducting pad to the bonding pad. A method thereof is also provided.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

Abstract: A method for forming a photosensitive module is provided. The method includes providing a sensing device. The sensing device includes a conducting pad located on a substrate. A first opening penetrates the substrate and exposes the conducting pad. A redistribution layer is in the first opening to electrically connect to the conducting pad. A cover plate is located on the substrate and covers the conducting pad. The method also includes removing the cover plate of the sensing device. The method further includes bonding the sensing device to a circuit board after the removal of the cover plate. The redistribution layer in the first opening is exposed and faces the circuit board. In addition, the method includes mounting an optical component corresponding to the sensing device on the circuit board. A photosensitive module formed by the method is also provided.