Patents by Inventor Yen Chan
Yen Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145381Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
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Publication number: 20240071944Abstract: The invention relates to the field of chip fabrication, in particular to the fabrication of superconducting integrated circuits for use in quantum computers. Raised and recessed alignment structures are provided on the surfaces of two substrate such that the raised and recessed alignment structure extends within the recessed alignment structure to a maximum depth determined by the geometry of the alignment structures. The alignment structures act as a hard stop for positioning and aligning the substrates for flip chip bonding.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Inventors: Máté JENEI, Kok Wai Chan, Kuan Yen Tan
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Patent number: 11916548Abstract: A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, an inverter, and a resistor-capacitor (RC) circuit coupled in series with the inverter between the input terminal and the output terminal. The RC circuit includes an NMOS transistor coupled between an RC circuit output terminal and a reference node, a resistor coupled between the RC circuit output terminal and a power supply node, and a capacitor coupled between the RC circuit output terminal and one of the power supply node or the reference node, and the inverter and the RC circuit are configured to generate an output signal at the output terminal based on the input signal.Type: GrantFiled: December 9, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wan-Yen Lin, Yuan-Ju Chan, Bo-Ting Chen
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Publication number: 20230422187Abstract: The transmission power at which to drive an antenna of a computing device is adjusted based on a peak transmission gain of the antenna for a current physical configuration mode in which the computing device is operating and on a maximum permitted radiation for the antenna. The antenna is driven at the adjusted transmission power when performing wireless communication using the antenna.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Inventors: Cheng-Fang Lin, Huai-Yung Yen, Ruei-Ting Lin, Ren-Hao Chen, Lo-Chun Tung, Sheng-Yen Chan, Hsiao Chun Su
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Patent number: 11770924Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.Type: GrantFiled: February 6, 2023Date of Patent: September 26, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
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Publication number: 20230189498Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
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Patent number: 11631679Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.Type: GrantFiled: May 10, 2022Date of Patent: April 18, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
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Patent number: 11522593Abstract: A method for selecting a beamforming technique, applied in an apparatus of a multi-cell network, provides optimization to maximize effective throughput of communication based on the multi-cell network, the optimization is modelled as a Markovian decision process, and a multi-agent reinforcement learning framework is built based on the multi-cell network. A multi-agent reinforcement learning algorithm is used to generate the optimization and obtain a current beamforming selection strategy of all base stations.Type: GrantFiled: January 21, 2022Date of Patent: December 6, 2022Assignee: HON LIN TECHNOLOGY CO., LTD.Inventors: Chia-Jung Fan, Chien-Jen Hwang, Ching-Ju Lin, Ping-Jung Hsieh, Tsung-Yen Chan
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Patent number: 11502180Abstract: A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile.Type: GrantFiled: February 17, 2020Date of Patent: November 15, 2022Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chia-Wei Wu, Ting-Pang Chung, Tien-Chen Chan, Shu-Yen Chan
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Publication number: 20220271037Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.Type: ApplicationFiled: May 10, 2022Publication date: August 25, 2022Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
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Patent number: 11393826Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.Type: GrantFiled: October 31, 2018Date of Patent: July 19, 2022Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
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Patent number: 10847517Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including of an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.Type: GrantFiled: June 18, 2019Date of Patent: November 24, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tsuo-Wen Lu, Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan
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Patent number: 10806046Abstract: A package structure of a power module is provided. The package structure includes a body having a sidewall, a first protruding structure protruding outward from one end of the sidewall, a second protruding structure protruding outward from another end of the sidewall and opposite to the first protruding structure, and a spring having two ends embedded in the first and the second protruding structures, respectively. The stress is transferred to the first and the second protruding structures via the spring, respectively. The equivalent stiffness of the spring is different from that of the body so that the package structure as a whole suffers the stress uniformly.Type: GrantFiled: October 22, 2019Date of Patent: October 13, 2020Assignee: Delta Electronics, Inc.Inventors: Shao-Chuan Chen, Hung-Yen Chan, Chuan-Chia Cheng, Hsueh-Kuo Liao, Kai-Ti Chang
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Publication number: 20200267867Abstract: A package structure of a power module is provided. The package structure includes a body having a sidewall, a first protruding structure protruding outward from one end of the sidewall, a second protruding structure protruding outward from another end of the sidewall and opposite to the first protruding structure, and a spring having two ends embedded in the first and the second protruding structures, respectively. The stress is transferred to the first and the second protruding structures via the spring, respectively. The equivalent stiffness of the spring is different from that of the body so that the package structure as a whole suffers the stress uniformly.Type: ApplicationFiled: October 22, 2019Publication date: August 20, 2020Inventors: Shao-Chuan CHEN, Hung-Yen CHAN, Chuan-Chia CHENG, Hsueh-Kuo LIAO, Kai-Ti CHANG
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Patent number: 10724140Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.Type: GrantFiled: July 31, 2018Date of Patent: July 28, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Chan Lo, Yi-Fang Lai, Po-Hsiung Leu, Ding-I Liu, Si-Wen Liao, Kai-Shiung Hsu, Jheng-Uei Hsieh, Shian-Huei Lin, Jui-Fu Hsu, Cheng-Tsung Wu
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Publication number: 20200185505Abstract: A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile.Type: ApplicationFiled: February 17, 2020Publication date: June 11, 2020Inventors: Chia-Wei Wu, Ting-Pang Chung, Tien-Chen Chan, Shu-Yen Chan
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Patent number: 10626499Abstract: A deposition device structure is provided. The deposition device structure includes a heater in a chamber. The deposition device structure also includes a shower head over the heater. The shower head includes holes extending from a top surface of the shower head to a bottom surface of the shower head. The bottom surface of the shower head faces the heater. The bottom surface of the shower head has a first section and a second section. The second section of the bottom surface is rougher than the first section of the bottom surface.Type: GrantFiled: October 5, 2017Date of Patent: April 21, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Chan Lo, Huan-Chieh Chen, Yi-Fang Lai, Keith Kuang-Kuo Koai, Chin-Feng Sun, Po-Hsiung Leu, Ding-I Liu, Kai-Shiung Hsu
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Patent number: 10608086Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate, at least one active area is defined on the substrate, a buried word line is disposed in the substrate, a source/drain region disposed beside the buried word line, a diffusion barrier region, disposed at the top of the source/drain region, the diffusion barrier region comprises a plurality of doping atoms selected from the group consisting of carbon atoms, nitrogen atoms, germanium atoms, oxygen atoms, helium atoms and xenon atoms, a dielectric layer disposed on the substrate, and a contact structure disposed in the dielectric layer, and electrically connected to the source/drain region.Type: GrantFiled: December 27, 2017Date of Patent: March 31, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan
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Patent number: 10608093Abstract: A semiconductor device and a method of forming the same are disclosed. First, a substrate having a main surface is provided. At least a trench is formed in the substrate. A barrier layer is formed in the trench and a conductive material is formed on the barrier layer and filling up the trench. The barrier layer and the conductive material are then recessed to be lower than the upper surface of the substrate. After that, an oxidation process is performed to oxidize the barrier layer and the conductive material thereby forming an insulating layer.Type: GrantFiled: January 18, 2018Date of Patent: March 31, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chia-Wei Wu, Ting-Pang Chung, Tien-Chen Chan, Shu-Yen Chan
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Patent number: 10497704Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.Type: GrantFiled: December 20, 2018Date of Patent: December 3, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Ger-Pin Lin, Kuan-Chun Lin, Chi-Mao Hsu, Shu-Yen Chan, Shih-Fang Tzou, Tsuo-Wen Lu, Tien-Chen Chan, Feng-Yi Chang, Shih-Kuei Yen, Fu-Che Lee