Abstract: A stage is provided for a receiver of a wireless device. The stage comprises a matching network that separates amplified signals of interest received from an amplifier from amplified unwanted signals received from the amplifier in conjunction with additional downstream filters. The stage also comprises a signal path that comprises components for receiving and processing the amplified signals of interest, and a shunt path that comprises components for adjusting reflected energy sent back to the amplifier for limiting the output swing of the amplifier in a frequency band corresponding to the amplified unwanted signals.

Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.

Abstract: A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface.

Abstract: A communications subsystem for a wireless device for correcting errors in a reference frequency signal. The communications subsystem comprises a frequency generator for generating the reference frequency signal and a closed loop reference frequency correction module that generates a reference frequency adjustment signal for correcting the reference frequency signal when the communications subsystem operates in closed loop mode. The subsystem further includes an open loop frequency correction means that that samples values of the reference frequency adjustment signal during the closed loop mode and generates a frequency correction signal for correcting the reference frequency signal when the communications subsystem operates in a mode other than closed loop mode.

Abstract: A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.

Abstract: Various embodiments described herein relate to a power management block and an amplification block used in the transmitter of a communication subsystem. The power management block provides improved control for the gain control signal provided to a pre-amplifier and the supply voltage provided to a power amplifier which are both in the amplification block. The power expended by the power amplifier is optimized by employing a continuous control method in which one or more feedback loops are employed to take into account various characteristics of the transmitter components and control values.

Abstract: A stage is provided for a receiver of a wireless device. The stage comprises a matching network that separates amplified signals of interest received from an amplifier from amplified unwanted signals received from the amplifier in conjunction with additional downstream filters. The stage also comprises a signal path that comprises components for receiving and processing the amplified signals of interest, and a shunt path that comprises components for adjusting reflected energy sent back to the amplifier for limiting the output swing of the amplifier in a frequency band corresponding to the amplified unwanted signals.

Abstract: A transmitter for a mobile device utilizes at least one mapper in order to improve power efficiency while still meeting out of band spurious emissions and waveform quality requirements. An encoder and modulator generates an encoded and modulated transmit signal from an input signal. A digital to analog converter coupled to the encoder and modulator generates an analog representation of the encoded and modulated transmit signal. An amplifier stage coupled to the digital to analog converter amplifies the analog representation of the encoded and modulated transmit signal to generate a transmission signal. The transmitter further comprises an amplifier control block configured to generate an amplifier control signal for adjusting at least one parameter of the amplifier stage. At least one mapper is provided in the amplifier control block, used to determine the amplifier control signal based on a peak to average power ratio and an average transmit power of the transmission signal.

Abstract: A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.

Abstract: A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an incident angle.

Abstract: A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor.

Abstract: A communications subsystem for a wireless device for correcting errors in a reference frequency signal. The communications subsystem comprises a frequency generator for generating the reference frequency signal and a closed loop reference frequency correction module that generates a reference frequency adjustment signal for correcting the reference frequency signal when the communications subsystem operates in closed loop mode. The subsystem further includes an open loop frequency correction means that that samples values of the reference frequency adjustment signal during the closed loop mode and generates a frequency correction signal for correcting the reference frequency signal when the communications subsystem operates in a mode other than closed loop mode.

Abstract: Various embodiments described herein relate to a power management block and an amplification block used in the transmitter of a communication subsystem. The power management block provides improved control for the gain control signal provided to a pre-amplifier and the supply voltage provided to a power amplifier which are both in the amplification block. The power expended by the power amplifier is optimized by employing a continuous control method in which one or more feedback loops are employed to take into account various characteristics of the transmitter components and control values.

Abstract: Various embodiments described herein relate to a power management block and an amplification block used in the transmitter of a communication subsystem. The power management block provides improved control for the gain control signal provided to a pre-amplifier and the supply voltage provided to a power amplifier which are both in the amplification block. The power expended by the power amplifier is optimized by employing a continuous control method in which one or more feedback loops are employed to take into account various characteristics of the transmitter components and control values.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region thereon; forming a high-k dielectric layer, a barrier layer, and a first metal layer on the substrate; removing the first metal layer of the second region; forming a polysilicon layer to cover the first metal layer of the first region and the barrier layer of the second region; patterning the polysilicon layer, the first metal layer, the barrier layer, and the high-k dielectric layer to form a first gate structure and a second gate structure in the first region and the second region; and forming a source/drain in the substrate adjacent to two sides of the first gate structure and the second gate structure.

Abstract: A power management system and method for a wireless communication device generates an average desired transmit power signal based on at least one of a received signal strength indicator signal and a power control instruction signal from a base station. A power supply level adjustment signal is generated based on the data parameters of an outgoing data stream and at least one environmental information signal. A combination of the power supply level adjustment signal and the average desired transmit power or a gain control signal and an altered version of the power supply level adjustment signal is used to generate a variable power supply signal that is provided to an output amplifier block for sufficiently generating outgoing wireless device radio signals while reducing power loss in the output amplifier block.

Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer.

Abstract: A process for forming a shallow trench isolation structure is provided. Firstly, a semiconductor substrate is provided. Then, a hard mask is formed over the semiconductor substrate, wherein the hard mask includes a pad oxide layer, a silicon nitride layer and an opening. Then, a trench is formed in the semiconductor substrate according to the opening Then, a pull-back process is performed to treat the silicon nitride layer at a sidewall of the opening, wherein the pull-back process is a wet etching process carried out in a phosphoric acid solution. After the pull-back process is performed, an insulating material is filled in the trench, thereby forming the shallow trench isolation structure.