Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate, at least one active area is defined on the substrate, a buried word line is disposed in the substrate, a source/drain region disposed beside the buried word line, a diffusion barrier region, disposed at the top of the source/drain region, the diffusion barrier region comprises a plurality of doping atoms selected from the group consisting of carbon atoms, nitrogen atoms, germanium atoms, oxygen atoms, helium atoms and xenon atoms, a dielectric layer disposed on the substrate, and a contact structure disposed in the dielectric layer, and electrically connected to the source/drain region.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; performing a first ion implantation process to form a first doped region having a first conductive type in the substrate adjacent to the trench; forming a gate electrode in the trench; and performing a second ion implantation process to form a second doped region having a second conductive type in the substrate above the gate electrode.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; performing an ion implantation process to implant ions into the substrate underneath the trench; performing an in-situ steam generation (ISSG) process to form a gate dielectric layer in the trench; forming a gate electrode on the gate dielectric layer; and forming a doped region in the substrate adjacent to two sides of the gate electrode.

Abstract: A dielectric structure and a manufacturing method thereof and a memory structure are provided. The dielectric structure includes a dielectric layer and a plurality of crystalline grains disposed in the dielectric layer. The dielectric layer includes a first high-K dielectric material with a first dielectric constant. Each crystalline grain includes a second high-K dielectric material with a second dielectric constant greater than the first dielectric constant and greater than 20. Each crystalline grain has a crystal structure, so that each crystalline grain has a third dielectric constant greater than the second dielectric constant. Whole dielectric constant of the dielectric structure can be raised by performing an annealing process to form the crystalline grains in the dielectric layer, and the capacity of the memory structure for storing electric charges can be increased.

Abstract: A method (500) performed by at least one server for processing a data packet from a first computing device to be transmitted to a second computing device is disclosed, in which the data packet includes a message encrypted using a first encryption key to form an encrypted message, identification data of the second computing device encrypted using a second encryption key to form encrypted identification data, and encrypted first and second encryption keys. The method comprises decrypting (504) the encrypted second encryption key; decrypting (506) the encrypted identification data using the decrypted second encryption key; and transmitting (508) the data packet based on the decrypted identification data, wherein the encrypted message and first encryption key are arranged to be undecryptable by the server to permit end-to-end encryption communication between the first and second computing devices. A related system is also disclosed.

Abstract: A method for fabricating semiconductor device is disclosed. First, a fin-shaped structure is formed on a substrate, a first liner is formed on the substrate and the fin-shaped structure, a second liner is formed on the first liner, part of the second liner and part of the first liner are removed to expose a top surface of the fin-shaped structure, part of the first liner between the fin-shaped structure and the second liner is removed to form a recess, and an epitaxial layer is formed in the recess.

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

Abstract: A method for fabricating semiconductor device is disclosed. First, a fin-shaped structure is formed on a substrate, a first liner is formed on the substrate and the fin-shaped structure, a second liner is formed on the first liner, part of the second liner and part of the first liner are removed to expose a top surface of the fin-shaped structure, part of the first liner between the fin-shaped structure and the second liner is removed to form a recess, and an epitaxial layer is formed in the recess.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor includes a substrate, two source/drain regions, a gate structure and two salicide layers. The two source/drain regions are partially disposed in the substrate each with a substantially flat top surface higher than a top surface of the substrate, and the two source/drain regions are separated from each other. The two source/drain regions are formed of an epitaxial material. The gate structure is disposed on the substrate between the two source/drain regions. The two salicide layers are disposed on the substantially flat top surfaces of the two source/drain regions, respectively.

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

Abstract: The present invention provides a metal oxide semiconductor (MOS) device, including a substrate, a gate structure on the substrate and a source/drain region disposed in the substrate at one side of the gate structure and in at least a part of an epitaxial structure, wherein the epitaxial structure includes a first buffer layer, which is an un-doped buffer layer, including a bottom portion disposed on a bottom surface of the epitaxial structure and a sidewall portion disposed on a concave sidewall of the epitaxial structure, an epitaxial layer which is encompassed by the first buffer layer, and a semiconductor layer which is disposed between the first buffer layer and the epitaxial layer. The source/drain region is disposed in the epitaxial structure.

Abstract: The present invention provides a method for forming a semiconductor structure, including: first, a substrate is provided. Next, at least two gate structures are formed on the substrate, each gate structure including two spacers disposed on two sides of the gate structure. Afterwards, a dry etching process is performed to remove parts of the substrate, so as to form a recess in the substrate, and a wet etching process is performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively. In addition, parts of the spacer are also removed through the wet etching process, and each spacer includes a rounding corner disposed on a bottom surface of the spacer.

Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.

Abstract: A method (500) performed by at least one server for processing a data packet from a first computing device to be transmitted to a second computing device is disclosed, in which the data packet includes a message encrypted using a first encryption key to form an encrypted message, identification data of the second computing device encrypted using a second encryption key to form encrypted identification data, and encrypted first and second encryption keys. The method comprises decrypting (504) the encrypted second encryption key; encryption key; decrypting (506) the encrypted identification data using the decrypted second encryption key; and transmitting (508) the data packet based on the decrypted identification data, wherein the encrypted message and first encryption key are arranged to be undecryptable by the server to permit end-to-end encryption communication between the first and recipient info encryption key end-to-end encryption communication between the first and second computing devices.

Abstract: A method for exchanging a message (202) between computing devices in a communication network, the message having encrypted data and a scheme identifier, is disclosed.

Abstract: Various embodiments described herein relate to a power management block and one or more amplification blocks used in the transmitter of a communication subsystem. The power management block provides improved control for the gain control signal provided to a pre-amplifier and the supply voltage provided to a power amplifier, both of which are included in a selected one of the amplification blocks. The power expended by the power amplifier is optimized by employing a continuous control method in which one or more feedback loops are employed to take into account various characteristics of the transmitter components and control values. Post power amplifier transmission power is detected for input into the one or more feedback loops executed in the power management block. A controller for the power amplifier is design to stabilize the system with respect to gain expansion in the power amplifier.

Abstract: Systems and methods to operate a power supply. A power supply has an inductor and a capacitor coupled in a substantially series connection. The power supply has a first selectably conductive path that selectably couples a first power pack to the series reactive circuit and a second selectably conductive path that selectably couples the series reactive circuit to a substantially series combination of the first power pack and a second power pack. When the first power pack output voltage is above the threshold, the first selectably conductive path couples electrical current between the first power pack to the series reactive circuit. Otherwise, the second selectably conductive path couples electrical current between the series combination and the series reactive circuit. The controller further transfers charge from the second power pack to the first power pack.

Abstract: A mobile wireless communications device may include an antenna, a wireless radio frequency (RF) receiver, a wireless RF transmitter, and a duplexer connecting the wireless RF receiver and the wireless RF transmitter to the antenna. More particularly, the wireless RF receiver may include a low noise amplifier (LNA) connected to the duplexer, a first receive signal chain for wireless communications signals having a first signal type downstream from the LNA, a second receive signal chain for wireless communications signals having a second signal type different than the first frequency band downstream from the LNA, and a power divider connecting the LNA to the first and second receive signal chains.

Abstract: A stage is provided for a receiver of a wireless device. The stage comprises a matching network that separates amplified signals of interest received from an amplifier from amplified unwanted signals received from the amplifier in conjunction with additional downstream filters. The stage also comprises a signal path that comprises components for receiving and processing the amplified signals of interest, and a shunt path that comprises components for adjusting reflected energy sent back to the amplifier for limiting the output swing of the amplifier in a frequency band corresponding to the amplified unwanted signals.