Patents by Inventor Yen-Hao Chen

Yen-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10867642
    Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsin-Cheng Chen, Jung-Rung Jiang, Yen-Hao Huang
  • Publication number: 20200388542
    Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHIANG, Chih-Hao WANG, Kuan-Lun CHENG, Yen-Ming CHEN
  • Patent number: 10854973
    Abstract: An antenna apparatus and an electronic apparatus are provided. The electronic apparatus includes the antenna apparatus. The antenna apparatus includes a radiator, a first and a second impedance control circuit. The radiator receives and transmits a radio frequency (RF) signal. The first impedance control circuit is electrically connected to the radiator and transmits the RF signal. The second impedance control circuit includes an impedance matching circuit and an inductor. The first end of the impedance matching circuit is electrically connected to the radiator. The impedance matching circuit adjusts the impedance matching of the radiator and transmits a sensing signal. The inductor is electrically connected to the second end of the impedance matching circuit. The inductor transmits a sensing signal, and blocks the RF signal. Accordingly, the structures of the antenna and the circuit can be simplified, and the influence between the RF signal and the sensing signal can be reduced.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 1, 2020
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: An-Yao Chou, Shih-Chia Liu, Yen-Hao Yu, Li-Chun Lee, Jhin-Ciang Chen, Chao-Lin Wu, Jui-Hung Lai
  • Patent number: 10833033
    Abstract: The present disclosure, in some embodiments, relates to a bump structure. The bump structure includes a conductive layer and a solder layer. The solder layer is disposed vertically below and laterally between portions of the conductive layer along a cross-section. The conductive layer is continuous between the portions.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen, Yen-Liang Lin
  • Publication number: 20200310250
    Abstract: Various methods are disclosed herein for reducing (or eliminating) printability of mask defects during lithography processes. An exemplary method includes performing a first lithography exposing process and a second lithography exposing process using a mask to respectively image a first set of polygons oriented substantially along a first direction and a second set of polygons oriented substantially along a second direction on a target. During the first lithography exposing process, a phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the first direction and a third direction that is different than the first direction. During the second lithography exposing process, the phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the second direction and a fourth direction that is different than the third direction.
    Type: Application
    Filed: June 12, 2020
    Publication date: October 1, 2020
    Inventors: Yen-Cheng Lu, Chia-Hao Hsu, Shinn-Sheng Yu, Chia-Chen Chen, Jeng-Horng Chen, Anthony Yen
  • Patent number: 10790321
    Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a floating diffusion region disposed at one side of a transfer gate within a substrate and a photo detecting column disposed at the other side of the transfer gate opposing to the floating diffusion region within the substrate. The photo detecting column comprises a doped sensing layer with a doping type opposite to that of the substrate. The photo detecting column and the substrate are in contact with each other at a junction interface comprising one or more recessed portions. By forming the junction interface with recessed portions, the junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Hsin-Chi Chen, Kuo-Cheng Lee, Ping-Hao Lin, Hsun-Ying Huang, Yen-Liang Lin, Yu Ting Kao
  • Patent number: 10788906
    Abstract: A manufacturing method of the flexible panel is provided. Firstly, a carrier substrate is provided. Then, an adhesion layer is formed on the carrier substrate, a flexible substrate is formed on the adhesion layer, and a buffer layer is formed on the flexible substrate. Then, a device layer is formed on the flexible substrate. Next, a separating process is performed for separating the flexible substrate and the device layer from the carrier substrate. According to a relation between a thermal expansion coefficient of the flexible substrate and a thermal expansion coefficient of the carrier substrate, the manufacturing method of the flexible panel selects a pattern of the adhesion layer. The pattern of the adhesion layer includes a frame adhesion structure or a plane adhesion structure.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 29, 2020
    Assignees: HannStar Display (Nanjing) Corporation, HANNSTAR DISPLAY CORPORATION
    Inventors: Yen-Chung Chen, Wei-Chih Hsu, Chen-Hao Su
  • Publication number: 20200304133
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Sandeep Kumar GOEL, Ji-Jan CHEN, Stanley JOHN, Yun-Han LEE, Yen-Hao HUANG
  • Patent number: 10766031
    Abstract: The present disclosure relates to a microfluidic-based analyzer, including a drive module and a microfluidic disc. On the microfluidic disk, a capillary is connected between a mixing chamber and a waste chamber. More particularly, the capillary is connected to the mixing chamber through a first access on the first radius of the microfluidic disc, and the capillary is connected to the waste chamber through a second access on the second radius of the microfluidic disk. Specifically, a turn of the capillary is disposed between the first access and the second access, in which a folding is configured on a third radius of the microfluidic disc. Overall, the aforementioned microfluidic-based analyzer is able to be operated in different rotational speeds and is capable of evacuating the mixing chamber and enhancing the washing efficiency.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: September 8, 2020
    Assignee: FENG CHIA UNIVERSITY
    Inventors: Chih-Hsin Shih, Ho-Chin Wu, Yen-Hao Chen
  • Patent number: 10771107
    Abstract: A circuit device includes a positive phase signal line, a negative phase signal line and a single-ended signal line. The positive phase signal line includes a first positive-phase-signal-line terminal and a second positive-phase-signal-line terminal for transmitting a first signal. The negative phase signal line includes a first negative-phase-signal-line terminal and a second negative-phase-signal-line terminal for transmitting a second signal. The single-ended signal line is disposed between the positive phase signal line and the negative phase signal line, and includes a first single-ended signal line terminal and a second single-ended signal line terminal for transmitting a single-ended signal. The first signal of the positive phase signal line causes a first noise on the single-ended signal line. The second signal of the negative phase signal line causes a second noise on the single-ended signal line. The first noise and the second noise eliminate one another.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: September 8, 2020
    Assignees: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventor: Yen-Hao Chen
  • Patent number: 10755983
    Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Lun Cheng, Yen-Ming Chen
  • Patent number: 10741926
    Abstract: A slot antenna structure for an electronic tag includes a dielectric layer, a conductor layer, a slot area and a capacitance adjustment unit. The electronic tag includes an identification chip. The conductor layer is disposed on the dielectric layer. The slot area is disposed in the conductor layer and includes an open slot, an open end and at least one closed slot. The open end is located at an edge of the conductor layer and extends inwardly to form the open slot for disposing the identification chip. The open slot has two sidewalls, and the two sidewalls have at least one turning point at a bottom portion of the open slot to form the closed slot. The capacitance adjustment unit is disposed on a surface of the dielectric layer different from the conductor layer to correspond to the slot area, thereby generating a capacitance effect.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: August 11, 2020
    Assignee: Compal Electronics, Inc.
    Inventors: Li-Chun Lee, Shih-Chia Liu, Yen-Hao Yu, Jhin-Ciang Chen, Chao-Lin Wu, Jui-Hung Lai
  • Patent number: 10732725
    Abstract: A method of interactive display based on gesture recognition includes determining a plurality of gestures corresponding to a plurality of images, interpreting a predetermined combination of gestures among the plurality of gestures as a command, and displaying a scene in response to the command.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: August 4, 2020
    Assignee: XRSpace CO., LTD.
    Inventors: Peter Chou, Feng-Seng Chu, Yen-Hung Lin, Shih-Hao Ke, Jui-Chieh Chen
  • Patent number: 10714394
    Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng, Yen-Ming Chen
  • Patent number: 10684552
    Abstract: Various methods are disclosed herein for reducing (or eliminating) printability of mask defects during lithography processes. An exemplary method includes performing a first lithography exposing process and a second lithography exposing process using a mask to respectively image a first set of polygons oriented substantially along a first direction and a second set of polygons oriented substantially along a second direction on a target. During the first lithography exposing process, a phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the first direction and a third direction that is different than the first direction. During the second lithography exposing process, the phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the second direction and a fourth direction that is different than the third direction.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Cheng Lu, Chia-Hao Hsu, Shinn-Sheng Yu, Chia-Chen Chen, Jeng-Horng Chen, Anthony Yen
  • Patent number: 10680627
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang
  • Patent number: 10678342
    Abstract: A method of virtual user interface interaction based on gesture recognition comprises detecting two hands in a plurality of images, recognizing each hand's gesture, projecting a virtual user interface on an open gesture hand when one hand is recognized with a point gesture and the other hand is recognized with an open gesture, tracking an index fingertip of the point gesture hand, determining whether the index fingertip of the point gesture hand is close to the open gesture hand within a predefined rule, interpreting a movement of the index fingertip of the point gesture hand as a click command when the index fingertip of the point gesture hand is close to the open gesture hand within the predefined rule, and in response to the click command, generating image data with a character object of the virtual user interface object.
    Type: Grant
    Filed: October 21, 2018
    Date of Patent: June 9, 2020
    Assignee: XRSpace CO., LTD.
    Inventors: Peter Chou, Feng-Seng Chu, Yen-Hung Lin, Shih-Hao Ke, Jui-Chieh Chen
  • Publication number: 20200163202
    Abstract: A noise suppression circuit device includes a baseboard, a decoupling capacitor set, a power bus structure, a band-stop filter unit and an electromagnetic band-gap structure. The decoupling capacitor set is disposed on the baseboard for isolating noise of a first frequency band. The power bus structure is disposed on the baseboard for isolating noise of a second frequency band. The band-stop filter unit is disposed on the baseboard for isolating at least a portion of noise of a third frequency band. The electromagnetic band-gap structure is disposed on the baseboard for isolating noise of a fourth frequency band.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 21, 2020
    Inventors: Yen-Hao Chen, Lin-Zong Zheng, Ding-Bing Lin, Min-Hung Hsieh
  • Publication number: 20200162126
    Abstract: A circuit device includes a positive phase signal line, a negative phase signal line and a single-ended signal line. The positive phase signal line includes a first positive-phase-signal-line terminal and a second positive-phase-signal-line terminal for transmitting a first signal. The negative phase signal line includes a first negative-phase-signal-line terminal and a second negative-phase-signal-line terminal for transmitting a second signal. The single-ended signal line is disposed between the positive phase signal line and the negative phase signal line, and includes a first single-ended signal line terminal and a second single-ended signal line terminal for transmitting a single-ended signal. The first signal of the positive phase signal line causes a first noise on the single-ended signal line. The second signal of the negative phase signal line causes a second noise on the single-ended signal line. The first noise and the second noise eliminate one another.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 21, 2020
    Inventor: Yen-Hao Chen
  • Publication number: 20200161764
    Abstract: A dual-band antenna is provided. The dual-band antenna includes a first antenna, a second antenna, and a grounding component. The first antenna has a first feed point for transceiving a first signal. The second antenna has a second feed point. The grounding component is electrically coupled to the first feed point and the second feed point, wherein the grounding component forms a first path and a second path between the first feed point and the second feed point, wherein a first path length of the first path and a second path length of the second path are integer multiples of a first wavelength of the first signal.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 21, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Wen-Jiao Liao, Jhin-Ciang Chen, Shih-Chia Liu, Liang-Che Chou, Yen-Hao Yu, Li-Chun Lee