Abstract: A system and a method for detecting abnormality of a thin-film deposition process are provided. In the method, a thin-film is deposited on a substrate in a thin-film deposition chamber by using a target, a dimension of a collimator mounted between the target and the substrate is scanned by using at least one sensor disposed in the thin-film deposition chamber to derive an erosion profile of the target, and abnormality of the thin-film deposition process is detected by analyzing the erosion profile with an analysis model trained with data of a plurality of erosion profiles derived under a plurality of deposition conditions.

Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: In a method of cleaning a lithography system, during idle mode, a stream of air is directed, through a first opening, into a chamber of a wafer table of an EUV lithography system. One or more particles is extracted by the directed stream of air from surfaces of one or more wafer chucks in the chamber of the wafer table. The stream of air and the extracted one or more particle are drawn, through a second opening, out of the chamber of the wafer table.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

Abstract: A bonding tool includes a gas supply line that may extend directly between valves associated with one or more gas supply tanks and a processing chamber such that gas supply line is uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line between the processing chamber and the valves associated with the one or more gas supply tanks. The pressure in the gas supply line may be maintained at or near the pressure in the processing chamber so that gas provided to the processing chamber through the gas supply line does not cause a pressure imbalance in the processing chamber, which might otherwise cause early or premature contact between semiconductor substrates that are to be bonded in the processing chamber.

Abstract: An antenna device and a method for configuring the same are provided. The antenna device includes a grounding metal, a grounding part, a radiating part, a feeding part, a proximity sensor, and a sensing metal. The radiating part is electrically connected to the grounding metal through the grounding part. The feeding part is coupled to the grounding metal through a feeding point. The sensing metal is electrically connected to the proximity sensor. The sensing metal is separated from the radiating part at a distance. The distance is less than or equal to one thousandth of a wavelength corresponding to an operating frequency of the antenna device.

Abstract: The present disclosure provides a multifunction chamber having a multifunctional shutter disk. The shutter disk includes a lamp device, a DC/RF power device, and a gas line on one surface of the shutter disk. With this configuration, simplifying the chamber type is possible as the various specific, dedicated chambers such as a degas chamber, a pre-clean chamber, a CVD/PVD chamber are not required. By using the multifunctional shutter disk, the degassing function and the pre-cleaning function are provided within a single chamber. Accordingly, a separate degas chamber and a pre-clean chamber are no longer required and the overall transfer time between chambers is reduced or eliminated.

Abstract: A magnetic assembly including a first magnetic core, a second magnetic core, a wire frame, multiple block magnetic cores, and a wire wrap is provided. The second magnetic core is assembled with the first magnetic core. The wire frame is disposed between the first magnetic core and the second magnetic core. The wire frame includes multiple accommodating spaces that are separated from each other, arranged at equal intervals, and have the same size. The block magnetic cores are respectively placed and fixed in the accommodating spaces of the wire frame in a drawer-like manner. The wire wrap is disposed around the wire frame, so as to wrap a part of the wire frame and the block magnetic cores in the wire wrap.

Abstract: A bonded assembly including a first structure and a second structure is provided. The first structure includes first metallic connection structures surrounded of which a passivation dielectric layer includes openings therein, and first metallic bump structures having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane including a distal horizontal surface of the passivation dielectric layer. The second structure includes second metallic bump structures having a respective second horizontal bonding surface segment that protrudes toward the first structure. The first metallic bump structures is bonded to the second metallic bump structures through solder material portions.

Abstract: Manufacturing method includes forming photoresist layer including photoresist composition over substrate. Photoresist composition includes: photoactive compound, polymer, crosslinker. The polymer structure A1, A2, A3 independently C1-C30 aryl, alkyl, cycloalkyl, hydroxylalkyl, alkoxy, alkoxyl alkyl, acetyl, acetylalkyl, carboxyl, alkyl carboxyl, cycloalkyl carboxyl, hydrocarbon ring, heterocyclic, chain, ring, 3-D structure; R1 is C4-C15 chain, cyclic, 3-D structure alkyl, cycloalkyl, hydroxylalkyl, alkoxy, or alkoxyl alkyl; proportion of x, y, and z in polymer is 0?x/(x+y+z)?1, 0?y/(x+y+z)?1, and 0?z/(x+y+z)?1, x, y, and z all not 0 for same polymer.

Abstract: A semiconductor structure includes a semiconductor die containing an array of first bonding structures. Each of the first bonding structures includes a first metal pad located within a dielectric material layer and a basin-shaped underbump metallization (UBM) pad located within a respective opening in a passivation dielectric layer and contacting the first metal pad. An interposer includes an array of second bonding structures, wherein each of the second bonding structures includes an underbump metallization (UBM) pillar having a respective cylindrical shape. The semiconductor die is bonded to the interposer through an array of solder material portions that are bonded to a respective one of the first-type bonding structures and to a respective one of the second-type bonding structures.

Abstract: A method for flattening an impedance of a power delivery network includes capturing a set of impedance parameters, obtaining an impedance of the power delivery network according to the set of impedance parameters, defining a target impedance, performing an importance calculation to determine a port, obtaining an intersection frequency according to the target impedance and the impedance of the power delivery network, selecting a decoupling capacitor according to the intersection frequency, and disposing the decoupling capacitor at the port. The method can reduce the impedance of the power delivery network to the target impedance and flatten the impedance to avoid the rogue wave phenomenon.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

Abstract: A semiconductor device, including a first gate, a second gate, a third gate, a first semiconductor layer, a second semiconductor layer, a source, and a drain, is provided. The first semiconductor layer is located between the first gate and the second gate. The second gate is located between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer is located between the second gate and the third gate. The source is electrically connected to the first semiconductor layer and the second semiconductor layer. The drain is electrically connected to the first semiconductor layer and the second semiconductor layer.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

Abstract: Novel photoresist additive compositions including developer solubility groups which enhance the solubility of the photoresist additive in a developer, such as a TMAH developer. The novel photoresist additive compositions also include functional groups to address outgassing and out-of-band issues.

Abstract: A method for examining differential pair transmission lines, performed by a processor, comprising: capturing a plurality of first insertion losses of a first signal line within a frequency range and a plurality of second insertion losses of a second signal line within the frequency range, wherein the first signal line and the second signal line are configured to transmit a pair of differential signals; calculating a plurality of maximum error ratios between the first insertion losses and the second insertion losses within the frequency range; determining whether any one of the maximum error ratios is greater than or equal to an upper threshold; outputting a warning signal when the processor determines one of the maximum error ratios is greater than or equal to the upper threshold; and ending the method when the processor determines each one of the maximum error ratios is smaller than the upper threshold.

Abstract: A method for flattening an impedance of a power delivery network includes capturing a set of impedance parameters, obtaining an impedance of the power delivery network according to the set of impedance parameters, defining a target impedance, performing an importance calculation to determine a port, obtaining an intersection frequency according to the target impedance and the impedance of the power delivery network, selecting a decoupling capacitor according to the intersection frequency, and disposing the decoupling capacitor at the port. The method can reduce the impedance of the power delivery network to the target impedance and flatten the impedance to avoid the rogue wave phenomenon.

Abstract: In a pattern formation method, a bottom layer is formed over an underlying layer. A middle layer is formed over the bottom layer. A resist pattern is formed over the middle layer. The middle layer is patterned by using the resist pattern as an etching mask. The bottom layer is patterned by using the patterned middle layer. The underlying layer is patterned. The middle layer contains silicon in an amount of 50 wt % or more and an organic material. In one or more of the foregoing and following embodiments, an annealing operation is further performed after the middle layer is formed.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.