Abstract: A resistive memory cell includes a lower electrode, a resistive transition metal oxide layer, and an upper electrode. The lower electrode includes at least one lower metallic barrier layer, a lower metal layer including a first metal having a melting point higher than 2,000 degrees Celsius, and a transition metal compound layer including an oxide or nitride of a transition metal selected from Ti, Ta, and W. The resistive transition metal oxide layer includes a conductive-filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer. The upper electrode includes an upper metal layer including a second metal having a melting point higher than 2,000 degrees Celsius and at least one upper metallic barrier layer.

Abstract: One or more semiconductor processing tools may deposit a contact etch stop layer on a substrate. In some implementations, the contact etch stop layer is comprised of less than approximately 12 percent hydrogen. Depositing the contact etch stop layer may include depositing contact etch stop layer material at a temperature of greater than approximately 600 degrees Celsius, at a pressure of greater than approximately 150 torr, and/or with a ratio of at least approximately 70:1 of NH3 and SiH4, among other examples. The one or more semiconductor processing tools may deposit a silicon-based layer above the contact etch stop layer. The one or more semiconductor processing tools may perform an etching operation into the silicon-based layer until reaching the contact etch stop layer to form a trench isolation structure.

Abstract: A deposition system is provided capable of controlling an amount of a target material deposited on a substrate and/or direction of the target material that is deposited on the substrate. The deposition system in accordance with the present disclosure includes a substrate process chamber. The deposition includes a substrate pedestal in the substrate process chamber, the substrate pedestal configured to support a substrate, a target enclosing the substrate process chamber, and a collimator having a plurality of hollow structures disposed between the target and the substrate, wherein a length of at least one of the plurality of hollow structures is adjustable.

Abstract: A method includes forming a first etch stop layer (ESL) over a conductive feature, forming a first dielectric layer on the first ESL, forming a second ESL on the first dielectric layer, forming a second dielectric layer on the second ESL, forming a trench in the second dielectric layer, forming a first opening in a bottom surface of the trench extending through the second dielectric layer, and forming a second opening in a bottom surface of the first opening. The second opening extends through the first dielectric layer and the first ESL. The second opening exposes a top surface of the conductive feature. The method further includes widening the first opening to a second width, filling the trench with a conductive material to form a conductive line, and filling the second opening and the first opening with the conductive material to form a conductive via.

Abstract: A thin film deposition system includes: a first precursor supply system configured to generate and supply a first precursor vapor from a first precursor source, the first precursor supply system comprising a first precursor source container, wherein at least a portion of an interior surface of the first precursor source container has a three-dimensional (3D) pattern, wherein the 3D pattern comprises a plurality of area enlarging elements configured to enlarge a total contact area of the interior surface of the first precursor source container with the first precursor source stored therein; and a deposition chamber in gas communication with the first precursor source container, the deposition chamber configured to receive the first precursor vapor and deposit a layer of a first precursor source onto a substrate placed in the deposition chamber.

Abstract: A cleaning device for cleaning particles from a tool includes a nozzle structure having a spray opening to spray a cleaning liquid in a first direction to the tool, a cleaning pad disposed around the nozzle structure, and a support disposed around the cleaning pad. The cleaning pad exposes the spray opening and includes a front surface facing in the first direction to clean the tool. The support includes multiple gas openings to blow a pressurized gas in the first direction to the tool, and multiple vacuum openings to suck residual gas, liquid and particles around the tool. An air wall around the tool is thus generated by a combination of operations performed by the multiple gas openings and the multiple vacuum openings to reduce or prevent contamination that might be caused by the cleaning device in the chamber.

Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Photoresist layer is selectively exposed to radiation, and selectively exposed photoresist layer developed. Photoresist composition includes photoactive compound, crosslinker, copolymer.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A substrate boat for use in heat treatment of semiconductor wafers includes support rods and fingers for supporting a substrate in a horizontal orientation in process tools, e.g., furnaces. The substrate is supported in the substrate boat by groups of fingers lying in a common horizontal plane. The fingers contact the substrate at support locations on the back side of the substrate. The fingers have a plurality of different shapes and a substrate surface no contact region.

Abstract: A sputtering target structure includes a back plate characterized by a first size and a plurality of sub-targets bonded to the back plate. Each of the sub-targets is characterized by a size that is a fraction of the first size and is no greater than a threshold target size. A given sub-target characterized by a size no greater than the threshold target size exhibits no crack formation in a sputtering operation. Each of the plurality of sub-targets is in direct contact with one or more adjacent sub targets.

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor device includes a first gate structure engaging a plurality of first channel members that are vertically stacked, a first source/drain feature abutting the first channel members, a second gate structure engaging a plurality of second channel members that are vertically stacked, a second source/drain feature abutting the second channel members, a first backside dielectric feature disposed directly under the first gate structure, and a second backside dielectric feature disposed directly under the second gate structure. A number of the first channel members is larger than a number of the second channel members. A top surface of the first backside dielectric feature is below a top surface of the second backside dielectric feature.

Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.

Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Photoresist layer is selectively exposed to radiation, and selectively exposed photoresist layer developed. Photoresist composition includes photoactive compound, crosslinker, copolymer.

Abstract: A memory circuit includes first and second memory segments coupled to first and second write lines, and first and second write line circuits coupled to the first and second write lines and configured to receive first and second data signals. The first and second data signals have complementary low and high logical states during a write operation to the first or second memory segment, and each of the first and second data signals has the low logical state during a masked write operation to the first or second memory segment. The first and second write line circuits output, to the first and second write lines, first and second write line signals responsive to the first and second data signals during the write operation and float the first and second data lines during the masked write operation.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features.

Abstract: A method for monitoring a shock wave in an extreme ultraviolet light source includes irradiating a target droplet in the extreme ultraviolet light source apparatus of an extreme ultraviolet lithography tool with ionizing radiation to generate a plasma and to detect a shock wave generated by the plasma. One or more operating parameters of the extreme ultraviolet light source is adjusted based on the detected shock wave.

Abstract: A first n-type transistor includes a first channel component, an undoped first gate dielectric layer disposed over the first channel component, and a first gate electrode disposed over the undoped first gate dielectric layer. A second n-type transistor includes a second channel component and a doped second gate dielectric layer disposed over the second channel component. The second gate dielectric layer is doped with a p-type dipole material. A second gate electrode is disposed over the second gate dielectric layer. At least one of the first n-type transistor or the second n-type transistor further includes an aluminum-free conductive layer. The aluminum-free conductive layer is disposed between the first gate dielectric layer and the first gate electrode or between the second gate dielectric layer and the second gate electrode.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes forming a stack of a first type and a second type epitaxial layers on a frontside of a semiconductor substrate, patterning the stack to form a fin-shaped structure, depositing a dielectric layer on sidewalls of the fin-shaped structure, and recessing the dielectric layer to expose a top portion of the fin-shaped structure. A top surface of the recessed dielectric layer is above a bottom surface of the stack. The exemplary manufacturing method also includes forming a gate structure over the top portion of the fin-shaped structure, etching the semiconductor substrate from a backside of the semiconductor substrate, and etching at least a bottommost first type epitaxial layer and a bottommost second type epitaxial layer through the trench.