Patents by Inventor Yen-Hao Chen

Yen-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190384172
    Abstract: Resist materials having enhanced sensitivity to radiation are disclosed herein, along with methods for lithography patterning that implement such resist materials. An exemplary resist material includes a polymer, a sensitizer, and a photo-acid generator (PAG). The sensitizer is configured to generate a secondary radiation in response to the radiation. The PAG is configured to generate acid in response to the radiation and the secondary radiation. The PAG includes a sulfonium cation having a first phenyl ring and a second phenyl ring, where the first phenyl ring is chemically bonded to the second phenyl ring.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 19, 2019
    Inventors: Yen-Hao Chen, Wei-Han Lai, Chien-Wei Wang, Chin-Hsiang Lin
  • Patent number: 10503214
    Abstract: The application discloses a support device, mounted in a portable electronic device, including an upper-cover shell, a base shell, and a pivot. The support device includes a cam structure, a first rod member, a second rod member, and a support member. The cam structure is connected to the pivot. The first pivot portion and the second pivot are pivotally connected to the base shell. The first rod member is in contact with the cam structure, and includes a first slide portion. The second rod member includes a second slide portion, movably connected to the first slide portion. The support member penetrates through an opening of the base shell, where a top surface of the support member and the second rod member are in contact with each other.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 10, 2019
    Assignee: PEGATRON CORPORATION
    Inventors: Cheng-Shi Jiang, Yen-Chi Kuo, Tzu-Ming Yang, Yu-Hao Chiu, Yu-Shu Zheng, Jeng-Hong Chiu, Chih-Ming Chen, Chih-Liang Chiang
  • Patent number: 10504856
    Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Chen, Yen-Liang Lin, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
  • Publication number: 20190371600
    Abstract: A method includes forming a photoresist layer over a substrate, where the photoresist layer includes a polymer blended with a photo-acid generator (PAG), exposing the photoresist layer to a radiation source, and developing the photoresist layer, resulting in a patterned photoresist layer. The PAG is bonded to one or more polarity-enhancing group (PEG), which is configured to increase a dipole moment of the PAG. The exposing may separate the PAG into a cation and an anion, such that a PEG bonded to the cation and a PEG bonded to the anion each increases a polarity of the cation and the anion, respectively.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Ya-Ching Chang, Ching-Yu Chang, Chin-Hsiang Lin, Yen-Hao Chen
  • Publication number: 20190348762
    Abstract: An antenna apparatus and an electronic apparatus are provided. The electronic apparatus includes the antenna apparatus. The antenna apparatus includes a radiator, a first and a second impedance control circuit. The radiator receives and transmits a radio frequency (RF) signal. The first impedance control circuit is electrically connected to the radiator and transmits the RF signal. The second impedance control circuit includes an impedance matching circuit and an inductor. The first end of the impedance matching circuit is electrically connected to the radiator. The impedance matching circuit adjusts the impedance matching of the radiator and transmits a sensing signal. The inductor is electrically connected to the second end of the impedance matching circuit. The inductor transmits a sensing signal, and blocks the RF signal. Accordingly, the structures of the antenna and the circuit can be simplified, and the influence between the RF signal and the sensing signal can be reduced.
    Type: Application
    Filed: May 13, 2019
    Publication date: November 14, 2019
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: An-Yao Chou, Shih-Chia Liu, Yen-Hao Yu, Li-Chun Lee, Jhin-Ciang Chen, Chao-Lin Wu, Jui-Hung Lai
  • Patent number: 10467364
    Abstract: In some embodiments, a plurality of first input waveforms having a same first input transition characteristic and different first tail characteristics are obtained. A first cell is characterized using the plurality of first input waveforms to create a plurality of corresponding first entries associated with the first input transition characteristic in a library. A design layout is generated based on performing circuit simulation using at least one entry of the plurality of first entries. An integrated circuit (IC) chip is manufactured using the design layout.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: King-Ho Tam, Yen-Pin Chen, Wen-Hao Chen, Chung-Hsing Wang
  • Publication number: 20190326240
    Abstract: The present disclosure, in some embodiments, relates to a bump structure. The bump structure includes a conductive layer and a solder layer. The solder layer is disposed vertically below and laterally between portions of the conductive layer along a cross-section. The conductive layer is continuous between the portions.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen, Yen-Liang Lin
  • Patent number: 10454167
    Abstract: An antenna structure includes a substrate, a metal element, and a feeding element. The metal element has an open slot. The open slot forms a first resonant path. The substrate is disposed on the metal element. The feeding element is disposed on the substrate, and the metal element and the feeding element are respectively disposed on two opposite sides of the substrate. The feeding element includes a feeding end and a shorting end electrically connected to the metal element. An orthogonal projection of the feeding element on the metal element is partially overlapped with the open slot. The feeding element forms a second resonant path extending from the feeding end to the shorting end. The antenna structure operates in a first band through the first resonant path and operates in a second band through the second resonant path.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 22, 2019
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yen-Hao Yu, Li-Chun Lee, Jui-Hung Lai, Shih-Chia Liu, Jhin-Ciang Chen, Chao-Lin Wu
  • Publication number: 20190304939
    Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
  • Publication number: 20190299402
    Abstract: An action teaching method is provided for teaching a robotic arm of a robotic arm system through a gesture teaching device. In a step (a), a touch condition of a user's finger is sensed by the touch sensing unit. In a step (b), a sensing result of the touch sensing unit is transmitted to an identification unit, so that a touch information is identified by the identification unit. In a step (c), the touch information is transmitted to a teaching unit, so that the teaching unit actuates a corresponding operation of the robotic arm system according to the touch information. In a step (d), an operating result of the robotic arm system is shown on a display unit, so that the user judges whether the operating result of the robotic arm system is successful through the display unit.
    Type: Application
    Filed: July 31, 2018
    Publication date: October 3, 2019
    Inventors: Ke-Hao Chang, Cheng-Hao Huang, Chun-Ying Chen, Yen-Po Wang
  • Publication number: 20190288067
    Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, a fin over the substrate and the isolation structure, a gate structure engaging a first portion of the fin, first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin, source/drain (S/D) features adjacent to the first sidewall spacers, and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers and the second portion of the fin include a same dopant.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 19, 2019
    Inventors: Chun Hsiung Tsai, Ya-Yun Cheng, Shahaji B. More, Cheng-Yi Peng, Wei-Yang Lee, Kuo-Feng Yu, Yen-Ming Chen, Jian-Hao Chen
  • Patent number: 10401728
    Abstract: Resist materials having enhanced sensitivity to radiation are disclosed herein, along with methods for lithography patterning that implement such resist materials. An exemplary resist material includes a polymer, a sensitizer, and a photo-acid generator (PAG). The sensitizer is configured to generate a secondary radiation in response to the radiation. The PAG is configured to generate acid in response to the radiation and the secondary radiation. The PAG includes a sulfonium cation having a first phenyl ring and a second phenyl ring, where the first phenyl ring is chemically bonded to the second phenyl ring.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Hao Chen, Wei-Han Lai, Chien-Wei Wang, Chin-Hsiang Lin
  • Patent number: 10394126
    Abstract: One of the broader forms of the present disclosure relates to a method of making a semiconductor device. The method includes exposing a photoresist layer to a radiation source and applying a hardening agent to the photoresist layer. Therefore after applying the hardening agent a first portion of the photoresist layer has a higher glass transition temperature, higher mechanical strength, than a second portion of the photoresist layer.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: August 27, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Ling Cheng, Ching-Yu Chang, Chien-Wei Wang, Yen-Hao Chen
  • Patent number: 10396156
    Abstract: A method includes providing a structure having a substrate, a fin, and a gate structure; performing an implantation process to implant a dopant into the fin adjacent to the gate structure; and forming gate sidewall spacers and fin sidewall spacers. The method further includes performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers. The method further includes performing another implantation process to implant the dopant into the fin and the fin sidewall spacers; and performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers. The method further includes epitaxially growing a semiconductor material in the trench.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Ya-Yun Cheng, Shahaji B. More, Cheng-Yi Peng, Wei-Yang Lee, Kuo-Feng Yu, Yen-Ming Chen, Jian-Hao Chen
  • Patent number: 10395999
    Abstract: A method for monitoring fin removal includes providing a substrate having a first region with first fins extending along a first direction and a second region with second fins extending along a second direction, wherein the first direction is perpendicular to the second direction; forming a material layer on the substrate to cover the first fins and the second fins; identically patterning the first fins and the second fins using a first pattern and a second pattern respectively for simultaneously removing parts of the first and second fins, thereby forming first fin features in the first region and second fin features in the second region, wherein the first pattern has a first dimension along the second direction, the second pattern has a second dimension along the second direction, and the second dimension is equal to the first dimension; and monitoring the first fin features using the second fin features.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 27, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hao Yang, En-Chiuan Liou, Hsiao-Lin Hsu, Tang-Chun Weng, Chia-Ching Lin, Yen-Pu Chen
  • Patent number: 10388622
    Abstract: In some embodiments, the present disclosure relates to a method of integrated chip bonding. The method is performed by forming a metal layer on a substrate, and forming a solder layer on the metal layer. The solder layer is reflowed. The metal layer and the solder layer have sidewalls defining a recess that is at least partially filled by the solder layer during reflowing of the solder layer.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 20, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen, Yen-Liang Lin
  • Publication number: 20190252347
    Abstract: A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Yen-Liang Lin, Chen-Shien Chen, Tin-Hao Kuo
  • Publication number: 20190237847
    Abstract: The disclosure provides an antenna module adapted for an electronic device having a metal casing. The antenna module includes an antenna structure and a slot structure. The antenna structure includes a radiation portion, a feeding portion, a ground portion and an extension portion, wherein the feeding portion, the ground portion and the extension portion are connected to the radiation portion. The slot structure has an open end and a closed end, wherein the open end of the slot structure is adjacent to the extension portion of the antenna structure. The antenna structure is excited and resonates to generate a first antenna resonant mode, and the slot structure is coupled to the antenna structure and resonates to generate a second antenna resonant mode.
    Type: Application
    Filed: January 21, 2019
    Publication date: August 1, 2019
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chao-Lin Wu, Shih-Chia Liu, Yen-Hao Yu, Li-Chun Lee, Jhin-Ciang Chen, Jui-Hung Lai
  • Publication number: 20190237543
    Abstract: A method includes providing a structure having a substrate, a fin, and a gate structure; performing an implantation process to implant a dopant into the fin adjacent to the gate structure; and forming gate sidewall spacers and fin sidewall spacers. The method further includes performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers. The method further includes performing another implantation process to implant the dopant into the fin and the fin sidewall spacers; and performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers. The method further includes epitaxially growing a semiconductor material in the trench.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 1, 2019
    Inventors: Chun Hsiung Tsai, Ya-Yun Cheng, Shahaji B. More, Cheng-Yi Peng, Wei-Yang Lee, Kuo-Feng Yu, Yen-Ming Chen, Jian-Hao Chen
  • Publication number: 20190229737
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Inventors: Sandeep Kumar GOEL, Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang