Abstract: The present disclosure provides a method for providing Quality of Service (QoS) processing of a plurality of data packets stored in a first memory. The method may include determining a queue of a plurality of queues causing an interrupt using contents of an interrupt status register, the queue comprising address of at least one data packet of the plurality of data packets. The method may further include performing a logical operation between the contents of the interrupt status register and an interrupt mask of a plurality of interrupt masks, the plurality of interrupt masks stored in a second memory. The method may also include processing the plurality of data packets based on the logical operation and incrementing an interrupt mask address pointer stored in a third memory, thereby pointing to another interrupt mask of the plurality of interrupt masks. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract: Various embodiments are directed to scalable and configurable queue management for network packet traffic Quality of Service (QoS). In one or more embodiments, the queue management may be implemented by a network processor comprising a queue manager to assert interrupts indicating that one or more queues require service, and a core processor to apply an interrupt mask to a status register value identifying the one or more queues that require service and to provide service during a particular service cycle to only those queues that are not masked out. Other embodiments are described and claimed.

Abstract: In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one access request involving a redundant array of independent disks (RAID) storage. The storage may be capable of accessing, in response, at least in part, to the at least one request an encryption and/or parity information. The encryption may be of at least one portion of the data and/or the parity information. The encryption may be stored in (1) encrypted disk stripes in the storage such that the data is unrecoverable based solely upon remaining unencrypted portion of the data and the parity information stored in the storage, and/or (2) one or more respective disk stripes having a number that is determined based at least in part upon one or more encryption levels, if any, associated with at least one characteristic of the data.

Abstract: Methods and systems for encrypting and decrypting are presented. In one embodiment, the method comprises encrypting one or more segments of a data with a key. The data is associated with at least one encryption attribute and having a plurality of segments. The encryption attribute includes information to identify one or more segments of the data to encrypt. The method further comprises encrypting the encryption attribute and storing the data including the partly encrypted data and the encrypted encryption attribute.

Abstract: Methods and apparatus for accessing a redundant array of independent drives (RAID) storage device are disclosed. In some embodiments file data is broken into multiple segments. A cryptographic operation is performed on one or more segments to generate encrypted segment(s). One or more parity syndrome is computed from the encrypted segment(s) and the unencrypted segment(s). The encrypted segment(s), the unencrypted segment(s) and the parity syndrome(s) are striped onto different individual drives. Since the cryptographic operation is not performed on all the segments, it may also be performed concurrently with computing of parity syndrome(s) from other unencrypted segments.

Abstract: Bandwidth is allocated among network interfaces of, for example, a switch, router, or server among based on network packet traffic. In one example the network device has a plurality of network interfaces, a performance monitoring unit to monitor buffer events for the network interfaces and to generate an interrupt if a network interface buffer is near an overflow state, and a processor to receive the interrupt and increase a priority of the associated network interface in response thereto.

Abstract: According to one embodiment, a method is disclosed. The method includes selecting a first of a plurality of programmable interrupt enable registers, a controller determining for the first register whether there interrupts at a queue manager to be processed by a processor, the processor reading an interrupt status register within the queue manager, the processor processing packets corresponding to addresses stored in each of a plurality of queues within the queue manager, selecting a second of a plurality of programmable interrupt enable registers and the controller determining for the second register whether there interrupts at the queue manager to be processed by the processor.

Abstract: The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.

Abstract: The present disclosure provides a method for providing Quality of Service (QoS) processing of a plurality of data packets stored in a first memory. The method may include determining a queue of a plurality of queues causing an interrupt using contents of an interrupt status register, the queue comprising address of at least one data packet of the plurality of data packets. The method may further include performing a logical operation between the contents of the interrupt status register and an interrupt mask of a plurality of interrupt masks, the plurality of interrupt masks stored in a second memory. The method may also include processing the plurality of data packets based on the logical operation and incrementing an interrupt mask address pointer stored in a third memory, thereby pointing to another interrupt mask of the plurality of interrupt masks. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract: In some embodiments, vertical controlled side chip connection for 3D processor package is presented. In this regard, an apparatus is introduced having a substrate, a substantially horizontal, in relation to the substrate, integrated circuit device coupled to the substrate, and a substantially vertical, in relation of the substrate, integrated circuit device coupled to the substrate and adjacent to one side of the substantially horizontal integrated circuit device. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus to provide die backside metallization and/or surface activated bonding for stacked die packages are described. In one embodiment, an active metal layer of a first die may be coupled to an active metal layer of a second die through silicon vias and/or a die backside metallization layer of the second die. Other embodiments are also described.

Abstract: Methods and apparatus to provide die backside connections are described. In one embodiment, the backside of a die is metallized and coupled to another die or a substrate. Other embodiments are also described.

Abstract: Various embodiments are directed to scalable and configurable queue management for network packet traffic Quality of Service (QoS). In one or more embodiments, the queue management may be implemented by a network processor comprising a queue manager to assert interrupts indicating that one or more queues require service, and a core processor to apply an interrupt mask to a status register value identifying the one or more queues that require service and to provide service during a particular service cycle to only those queues that are not masked out. Other embodiments are described and claimed.

Abstract: According to one embodiment, a method is disclosed. The method includes selecting a first of a plurality of programmable interrupt enable registers, a controller determining for the first register whether there interrupts at a queue manager to be processed by a processor, the processor reading an interrupt status register within the queue manager, the processor processing packets corresponding to addresses stored in each of a plurality of queues within the queue manager, selecting a second of a plurality of programmable interrupt enable registers and the controller determining for the second register whether there interrupts at the queue manager to be processed by the processor.