Abstract: Methods and systems for encrypting and decrypting are presented. In one embodiment, the method comprises encrypting one or more segments of a data with a key. The data is associated with at least one encryption attribute and having a plurality of segments. The encryption attribute includes information to identify one or more segments of the data to encrypt. The method further comprises encrypting the encryption attribute and storing the data including the partly encrypted data and the encrypted encryption attribute.

Abstract: Apparatuses and methods of swapping pointers to process data stored in a plurality of buffers by a data source without copying the data to separate storage are provided. Data may be consecutively loaded into a plurality of buffers pointed to by a first pointer by consecutively swapping the first pointer to point to the plurality of buffers. The data loaded in the plurality of buffers can be consecutively processed by consecutively pointing a second pointer to the plurality of buffers by consecutively swapping the second pointer to point to the plurality of buffer.

Abstract: A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache memories. A first cache memory associated a first of the execution cores includes a plurality of cache lines. The first cache memory has a cache controller including hardware logic, microcode, or both to identify a first cache line as an interrupt reserved cache line and map the first cache line to a host physical memory address translated from a guest physical memory address in the address space of a virtual machine to which an I/O device has been assigned. The controller may set a coherency state of the first cache line to shared and, in response to detecting an I/O transaction including I/O data from the I/O device and containing a reference to the host physical memory address, emulate a first message signaled interrupt identifying the host physical memory address.

Abstract: Methods and systems for encrypting and decrypting are presented. In one embodiment, the method comprises encrypting one or more segments of a data with a key. The data is associated with at least one encryption attribute and having a plurality of segments. The encryption attribute includes information to identify one or more segments of the data to encrypt. The method further comprises encrypting the encryption attribute and storing the data including the partly encrypted data and the encrypted encryption attribute.

Abstract: Methods and apparatuses to reduce the number of read/write operations performed by a CPU may involve duplicating source data to enable parallel processing on the source data. A memory controller may be configured to duplicate data written to a first buffer to one or more duplicate buffers that are allocated to one or more processing threads, respectively. In some implementations, the one or more duplicate buffers are dedicated buffers, and the addresses of the first buffer and the one or more duplicate buffers are stored in a register of memory controller.

Abstract: Methods to emulate a message signaled interrupt (MSI) with interrupt data are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory block allocated to a device, an interrupt controller to receive an emulated messaged signaled interrupt (MSI) signal from the memory decoder in response to a posted write transaction to the predetermined memory block initiated from the device, and an execution unit to execute an interrupt service routine (ISR) associated with the device to service the MSI using interrupt data retrieved from the predetermined memory block, without having to obtain the interrupt data from the device via an input output (IO) transaction.

Abstract: Embodiments of an apparatus, system and method are described for managing one or more solar cells for a mobile computing device. An apparatus may comprise, for example, a power management module operative to manage a power output received from a plurality of solar cells and an interface management module operative to identify one or more solar cells having a lower power output than other solar cells and to adjust one or more graphical user interface (GUI) elements based on the identification. Other embodiments are described and claimed.

Abstract: Methods and systems may provide for identifying a proximity condition between a system and a potential user of the system. In addition, one or more boot components of the system can be activated in response to the proximity condition, wherein one or more peripheral devices associated with the system are maintained in an inactive state. In one example, at least one of the one or more peripheral devices is placed in an active state in response to detecting an activation condition of the system.

Abstract: Methods and apparatus relating to network routing protocols to support power savings in network elements. A most utilized link path network topology for a computer network is discovered using a routing protocol such as a Spanning Tree, link-state, or distance vector routing protocol. In view of the most utilized link path network topology, links are identified as candidates for power management under which a power state of the link and associated network ports are managed to save power under applicable link conditions, such as low utilization. Link power-state change conditions are detected, and in response a corresponding change to the power state of a link is effected by changing the power-state of the network ports at the ends of the link. Power state changes include putting a link into a reduced power state, taking a link offline, and powering a link back up.

Abstract: Methods to accelerate a message signaled interrupt (MSI) are described herein. An embodiment of the invention includes an interrupt controller to receive a messaged signaled interrupt (MSI) request from a device over a bus, and an execution unit coupled to the interrupt controller to execute an interrupt service routine (ISR) associated with the device, the execution unit to retrieve interrupt data from a predetermined memory location specifically allocated to the device and to service the MSI using the interrupt data, without having to obtain the device interrupt data via an input output (IO) transaction.

Abstract: The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.

Abstract: A method and system for combining print jobs is described herein. The method includes loading a print surface containing a first print job and obtaining a second print job. The first print job and the second print job may be combined into a composite file, wherein the composite file is used to adjust the first print job and the second print job.

Abstract: A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache memories. A first cache memory associated a first of the execution cores includes a plurality of cache lines. The first cache memory has a cache controller including hardware logic, microcode, or both to identify a first cache line as an interrupt reserved cache line and map the first cache line to a selected memory address associated with an I/O device. The selected system address may be a portion of configuration data in persistent storage accessible to the processor. The controller may set a coherency state of the first cache line to shared and, in response to detecting an I/O transaction including I/O data from the I/O device and containing a reference to the selected memory address, emulate a first message signaled interrupt identifying the selected memory address.

Abstract: The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.

Abstract: Apparatuses, systems, and methods are directed to securely store, transfer, and/or process data especially sensitive data sent from input devices to processors. In one embodiment, sensitive data may be packaged with at least one interrupt vector to provide a single posted write transaction initiated by an input device. The single posted write transaction may then be directly sent to a predetermined memory block allocated from a processor. In response to the single posted write transaction, a memory decoder associated with the processor may generate an emulated message signaled interrupt (MSI) signal to invoke an interrupt handler or an interrupt service routine (ISR) to service the emulated MSI using interrupt data, including the sensitive data, retrieved from the predetermined memory block. Once the sensitive data are processed by the processor, they may be removed from the processor before the processor exits the interrupt handler.

Abstract: A system and method for monitoring a data-path between a plurality of devices which are communicably interfaced with a bus for a transaction. The transaction is copied to a replicate transaction, and the original transaction is allowed to proceed to whichever of the plurality of devices to which it is uniquely addressed according to the transaction. A destination address of the replicate transaction is modified to a specified memory device which is also communicably interfaced with the bus, and the replicate transaction is then released onto the data-path, thus allowing the replicate transaction to proceed to the specified memory device based on the modified destination address.

Abstract: Examples are disclosed for video analytics of captured video content. In some examples, information may be received from a host processing system for a camera to capture video content. The camera may be a surveillance camera or a camera located with a display device. Video analytics may be performed on the captured video and the captured video content may be encoded. Data associated with the video analytics may then be sent to the host processing system. In some examples, the data as well as encoded captured video content or streaming video may be sent via communication channels included in an interconnect. Other examples are described and claimed.

Abstract: A method and apparatus may detect an event related to an external device communicating with a host controller. One or more external device characteristics of the external device may be determined. One or more physical memory cells for the host controller may be modified based on the one or more external device characteristics.

Abstract: An embodiment includes a system recognizing a first user via a camera, selecting a profile for the first user, and interpreting the first user's gestures according to that profile. For example, the embodiment identifies a first user, loads his gesture signature profile, and then interprets the first user forming his fist with his thumb projecting upwards as acceptance of a condition presented to the user (e.g., whether the user wishes to turn a tuner to a certain channel). The embodiment recognizes a second user, selects a profile for the second user, and interprets the second user's gestures according to that profile. For example, the embodiment identifies the second user, loads her profile, and then interprets the second user forming her fist with her thumb projecting upwards as the user pointing upwards. This moves an area of focus upwards on a graphical user interface. Other embodiments are described herein.

Abstract: In an embodiment, a processor includes a logic to store a write transaction including an interrupt and data received from a device coupled to the processor to a cache line of a cache memory based on an address in an address queue, and forward an address of the cache line and assert an emulated message signaling interrupt (MSI) signal to an interrupt controller of the processor. Other embodiments are described and claimed.