Abstract: Imaging system management is described for a camera mounted behind a transparent display. In one example, the management includes determining whether an image sensor behind a transparent display is in an image capture mode, and if the image sensor is in an image capture mode then setting pixels of a sensor region of the display to a transparent mode during the image capture mode, the pixels of the sensor region comprising pixels of the display in a region around the image sensor. The management further includes determining whether the image sensor has finished the image capture mode, and if the image sensor has finished the image capture mode then setting the pixels of the display in the region around the image sensor to a display mode in which the pixels render a portion of an image on the display.

Abstract: An embodiment may include determining at least one respective amount of buffer memory to be used to store at least one respective portion of network traffic. The determining may be based at least in part upon at least one respective parameter associated with the at least one respective network traffic portion. The at least one respective amount may be sufficient to store the at least one respective portion of the network traffic. The at least one respective parameter may reflect at least one actual characteristic of the at least one respective portion of the network traffic. This embodiment also may permit at least one respective portion of the buffer memory that may correspond to the at least one respective amount to be selectively powered-on to permit the at least one portion of the buffer memory to be used to store the at least one respective network traffic portion.

Abstract: An object that has attracted a viewer's interest is determined using head pose and distance information. In one example a viewer's head is detected at a camera of a computing system. A distance from the head to the camera is determined. A pose of the head is determined as a yaw angle of the head. A location is determined using the distance and the yaw angle, and an object of attention is determined using the location.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.

Abstract: Technologies for secure I/O redirection include a provider device, a consumer device, an authentication server, and a messaging server. The provider device and the consumer device establish an authenticated I/O redirect pairing. The authentication server authenticates the consumer device, and, if authenticated, generates a pairing identifier and provides the pairing identifier to the provider device and the consumer device. The redirect pairing is associated with the shared pairing identifier, a shared encryption key, and one or more shared message topics. The provider device and the consumer device subscribe to the messaging server as publisher and/or listener using the shared message topics. The provider device and the consumer device encrypt I/O data using the shared encryption key and encapsulate the encrypted I/O data into messages using the shared message topics. The provider device and the consumer device exchange the messages using the messaging server. Other embodiments are described and claimed.

Abstract: Embodiments of wearable electronic devices, components thereof, and related systems and techniques are disclosed herein. For example, a wearable electronic device may include a wearable support structure having a first surface and a second surface; a first electrode located at the first surface, wherein, when the wearable electronic device is worn by a user on a portion of the user's body, the first electrode is arranged to contact the user's skin in the portion of the user's body; a second electrode located at the second surface, wherein, when the wearable electronic device is worn by a user on the portion of the user's body, the second electrode is arranged to not contact the user's skin in the portion of the user's body; and a resistance switch having first and second input terminals coupled to the first and second electrodes, respectively. Other embodiments may be disclosed and/or claimed.

Abstract: Methods to emulate a message signaled interrupt (MSI) with multiple interrupt vectors are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory location allocated to a device and to generate an emulated message signaled interrupt (MSI) signal in response to a posted write transaction to the predetermined memory location initiated from the device, and an interrupt controller, in response to the emulated MSI signal from the memory decoder, to invoke processing of a plurality of interrupts based on a plurality of interrupt vectors retrieved from the predetermined memory location, without receiving an actual MSI interrupt request from the device.

Abstract: A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache memories. A first cache memory associated a first of the execution cores includes a plurality of cache lines. The first cache memory has a cache controller including hardware logic, microcode, or both to identify a first cache line as an interrupt reserved cache line and map the first cache line to a host physical memory address translated from a guest physical memory address in the address space of a virtual machine to which an I/O device has been assigned. The controller may set a coherency state of the first cache line to shared and, in response to detecting an I/O transaction including I/O data from the I/O device and containing a reference to the host physical memory address, emulate a first message signaled interrupt identifying the host physical memory address.

Abstract: Methods to accelerate a message signaled interrupt (MSI) are described herein. An embodiment of the invention includes an interrupt controller to receive a messaged signaled interrupt (MSI) request from a device over a bus, and an execution unit coupled to the interrupt controller to execute an interrupt service routine (ISR) associated with the device, the execution unit to retrieve interrupt data from a predetermined memory location specifically allocated to the device and to service the MSI using the interrupt data, without having to obtain the device interrupt data via an input output (IO) transaction.

Abstract: Examples are disclosed for video analytics of captured video content. In some examples, information may be received from a host processing system for a camera to capture video content. The camera may be a surveillance camera or a camera located with a display device. Video analytics may be performed on the captured video and the captured video content may be encoded. Data associated with the video analytics may then be sent to the host processing system. In some examples, the data as well as encoded captured video content or streaming video may be sent via communication channels included in an interconnect. Other examples are described and claimed.

Abstract: Apparatuses, systems, and methods are directed to securely store, transfer, and/or process data especially sensitive data sent from input devices to processors. In one embodiment, sensitive data may be packaged with at least one interrupt vector to provide a single posted write transaction initiated by an input device. The single posted write transaction may then be directly sent to a predetermined memory block allocated from a processor. In response to the single posted write transaction, a memory decoder associated with the processor may generate an emulated message signaled interrupt (MSI) signal to invoke an interrupt handler or an interrupt service routine (ISR) to service the emulated MSI using interrupt data, including the sensitive data, retrieved from the predetermined memory block. Once the sensitive data are processed by the processor, they may be removed from the processor before the processor exits the interrupt handler.

Abstract: Embodiments of methods and systems for encrypting and decrypting with encryption attributes are presented. An encryption attribute contains information to identify one or more segments of a file to be encrypted. An encryption process encrypts those one or more segments to generate a partly encrypted file instead of encrypting the entire file. That is, the file includes some data that are encrypted and some data that are not. In one embodiment, at least three encryption keys are used such that the encryption attribute is encrypted with using a third key.

Abstract: A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache memories. A first cache memory associated a first of the execution cores includes a plurality of cache lines. The first cache memory has a cache controller including hardware logic, microcode, or both to identify a first cache line as an interrupt reserved cache line and map the first cache line to a selected memory address associated with an I/O device. The selected system address may be a portion of configuration data in persistent storage accessible to the processor. The controller may set a coherency state of the first cache line to shared and, in response to detecting an I/O transaction including I/O data from the I/O device and containing a reference to the selected memory address, emulate a first message signaled interrupt identifying the selected memory address.

Abstract: Technologies for secure user authentication include a computing device with a touch screen display coupled to an electronic paper display, and a security engine isolated from a host processor. To process a payment transaction, the computing device invokes the security engine to generate a random virtual keypad layout that is not accessible by the host processor. The virtual keypad layout includes virtual keypad buttons that may be randomly positioned. The security engine displays the virtual keypad layout on the electronic paper display that overlays the touch screen display. The computing device detects touch input using the touch screen and transmits the touch input to the security engine. The security engine determines keypad input based on the touch input by mapping coordinates of the touch input to virtual buttons of the virtual keypad. The security engine authorizes the transaction based on the keypad input. Other embodiments are described and claimed.

Abstract: Embodiments of methods and systems for encrypting and decrypting with encryption attributes are presented. An encryption attribute contains information to identify one or more segments of a file to be encrypted. An encryption process encrypts those one or more segments to generate a partly encrypted file instead of encrypting the entire file. That is, the file includes some data that are encrypted and some data that are not. In one embodiment, at least three encryption keys are used such that the encryption attribute is encrypted with using a third key.

Abstract: Methods and apparatus relating to network routing protocols to support power savings in network elements. A most utilized link path network topology for a computer network is discovered using a routing protocol such as a Spanning Tree, link-state, or distance vector routing protocol. In view of the most utilized link path network topology, links are identified as candidates for power management under which a power state of the link and associated network ports are managed to save power under applicable link conditions, such as low utilization. Link power-state change conditions are detected, and in response a corresponding change to the power state of a link is effected by changing the power-state of the network ports at the ends of the link. Power state changes include putting a link into a reduced power state, taking a link offline, and powering a link back up.

Abstract: Embodiments of computer-implemented methods, systems, apparatuses, and computer-readable media (transitory and non-transitory) are described herein for configuring a self-service computing device to provide, to a remote computing device in direct wireless communication with the self-service computing device, data for the remote computing device to render an instance of a user interface operable by a user of the remote computing device to select a product or service offered by the self-service computing device. Other embodiments may be described and/or claimed.

Abstract: The disclosure generally relates to a method, system and apparatus for establishing a secure ad-hoc network. In one embodiment, the disclosure provides a method for establishing an ad-hoc network by: generating a security key at a first device and communicating the security key to a second device using a first communication channel; selecting a network protocol supported by both the first and the second device; exchanging networking information for establishing a second communication channel using the first communication channel, the second communication channel defining an ad-hoc network; and establishing the second communication channel between the first and the second device using the selected network protocol.

Abstract: Techniques and mechanisms for assuring that one or more addressable locations in memory of a computer platform are transitioned from potentially invalid state to known-valid state. In an embodiment, a memory validation agent separate from a processor of the computer platform performs memory validation writes in response to an indication of power state transition. In another embodiment, the memory validation agent determines information to be included in write commands which implement the memory validation, where the determining the information is decoupled from operation of the processor.

Abstract: Methods to emulate a message signaled interrupt (MSI) with interrupt data are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory block allocated to a device, an interrupt controller to receive an emulated messaged signaled interrupt (MSI) signal from the memory decoder in response to a posted write transaction to the predetermined memory block initiated from the device, and an execution unit to execute an interrupt service routine (ISR) associated with the device to service the MSI using interrupt data retrieved from the predetermined memory block, without having to obtain the interrupt data from the device via an input output (IO) transaction.