Abstract: Methods to emulate a message signaled interrupt (MSI) with multiple interrupt vectors are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory location allocated to a device and to generate an emulated message signaled interrupt (MSI) signal in response to a posted write transaction to the predetermined memory location initiated from the device, and an interrupt controller, in response to the emulated MSI signal from the memory decoder, to invoke processing of a plurality of interrupts based on a plurality of interrupt vectors retrieved from the predetermined memory location, without receiving an actual MSI interrupt request from the device.

Abstract: Techniques and mechanisms for assuring that one or more addressable locations in memory of a computer platform are transitioned from potentially invalid state to known-valid state. In an embodiment, a memory validation agent separate from a processor of the computer platform performs memory validation writes in response to an indication of power state transition. In another embodiment, the memory validation agent determines information to be included in write commands which implement the memory validation, where the determining the information is decoupled from operation of the processor.

Abstract: An embodiment may include determining at least one respective amount of buffer memory to be used to store at least one respective portion of network traffic. The determining may be based at least in part upon at least one respective parameter associated with the at least one respective network traffic portion. The at least one respective amount may be sufficient to store the at least one respective portion of the network traffic. The at least one respective parameter may reflect at least one actual characteristic of the at least one respective portion of the network traffic. This embodiment also may permit at least one respective portion of the buffer memory that may correspond to the at least one respective amount to be selectively powered-on to permit the at least one portion of the buffer memory to be used to store the at least one respective network traffic portion.

Abstract: Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.

Abstract: In accordance with some embodiments, background subtraction can be performed by iteratively computing a new expected background image from an old background image using a plurality of consecutive frames. The new expected background image may be computed to be closer to a current frame's pixel value. In some embodiments, a new expected background image may be based on user supplied values so that a user may determine how fast a background image changes.

Abstract: Methods and apparatus for accessing a redundant array of independent drives (RAID) storage device are disclosed. In some embodiments file data is broken into multiple segments. A cryptographic operation is performed on one or more segments to generate encrypted segment(s). One or more parity syndrome is computed from the encrypted segment(s) and the unencrypted segment(s). The encrypted segment(s), the unencrypted segment(s) and the parity syndrome(s) are striped onto different individual drives. Since the cryptographic operation is not performed on all the segments, it may also be performed concurrently with computing of parity syndrome(s) from other unencrypted segments.

Abstract: Methods and apparatus to provide die backside connections are described. In one embodiment, the backside of a die is metallized and coupled to another die or a substrate. Other embodiments are also described.

Abstract: An apparatus to protect contents of a memory region is presented. In one embodiment, the apparatus includes a non-volatile memory, memory check logic to generate check values for protected memory regions, and comparison logic to compare stored check values from the non-volatile memory with generated check values from the memory check logic. The apparatus also includes security logic to prevent executing code in the protected memory regions if the comparison logic detects a mismatch between the stored check values and the generated check values.

Abstract: Embodiments of methods and systems for encrypting and decrypting with encryption attributes are presented. An encryption attribute contains information to identify one or more segments of a file to be encrypted. An encryption process encrypts those one or more segments to generate a partly encrypted file instead of encrypting the entire file. That is, the file includes some data that are encrypted and some data that are not. In one embodiment, at least three encryption keys are used such that the encryption attribute is encrypted with using a third key.

Abstract: Methods and apparatus to provide die backside metallization and/or surface activated bonding for stacked die packages are described. In one embodiment, an active metal layer of a first die may be coupled to an active metal layer of a second die through silicon vias and/or a die backside metallization layer of the second die. Other embodiments are also described.

Abstract: A method and apparatus may detect an event related to an external device communicating with a host controller. One or more external device characteristics of the external device may be determined. One or more physical memory cells for the host controller may be modified based on the one or more external device characteristics.

Abstract: The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.

Abstract: Embodiments of the invention utilize a signal analyzer to monitor a data path, the data path to include a plurality of transactions to be executed via a processor. The signal analyzer may further identify data of a first and a second transaction from the plurality of transactions. Transaction replication logic operatively coupled to the signal analyzer may generate a replicate transaction from the first transaction in response to the signal analyzer identifying the data of the first transaction, the replicate transaction to be stored in a memory. An interrupt generator operatively coupled to the signal analyzer may send an interrupt to the processor in response to the signal analyzer identifying at least the data of the second transaction, the processor to halt the execution of transactions and to pass control of execution of the second transaction to a debugging module in response to receiving the interrupt.

Abstract: In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one access request involving a redundant array of independent disks (RAID) storage. The storage may be capable of accessing, in response, at least in part, to the at least one request an encryption and/or parity information. The encryption may be of at least one portion of the data and/or the parity information. The encryption may be stored in (1) encrypted disk stripes in the storage such that the data is unrecoverable based solely upon remaining unencrypted portion of the data and the parity information stored in the storage, and/or (2) one or more respective disk stripes having a number that is determined based at least in part upon one or more encryption levels, if any, associated with at least one characteristic of the data.

Abstract: The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.

Abstract: An apparatus comprises logic to manage data access in an electronic device by performing operations, comprising detecting at least one of a motion, vibration or change in orientation of the electronic device and in response to a detection, implementing a security policy for the electronic device. Other embodiments may be described.

Abstract: A system and method for monitoring a data-path between a plurality of devices which are communicably interfaced with a bus for a transaction. The transaction is copied to a replicate transaction, and the original transaction is allowed to proceed to whichever of the plurality of devices to which it is uniquely addressed according to the transaction. A destination address of the replicate transaction is modified to a specified memory device which is also communicably interfaced with the bus, and the replicate transaction is then released onto the data-path, thus allowing the replicate transaction to proceed to the specified memory device based on the modified destination address.

Abstract: Bandwidth is allocated among network interfaces of, for example, a switch, router, or server among based on network packet traffic. In one example the network device has a plurality of network interfaces, a performance monitoring unit to monitor buffer events for the network interfaces and to generate an interrupt if a network interface buffer is near an overflow state, and a processor to receive the interrupt and increase a priority of the associated network interface in response thereto.

Abstract: Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.

Abstract: The present disclosure provides a method for providing Quality of Service (QoS) processing of a plurality of data packets stored in a first memory. The method may include determining a queue of a plurality of queues causing an interrupt using contents of an interrupt status register, the queue comprising address of at least one data packet of the plurality of data packets. The method may further include performing a logical operation between the contents of the interrupt status register and an interrupt mask of a plurality of interrupt masks, the plurality of interrupt masks stored in a second memory. The method may also include processing the plurality of data packets based on the logical operation and incrementing an interrupt mask address pointer stored in a third memory, thereby pointing to another interrupt mask of the plurality of interrupt masks. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.