Patents by Inventor Yen-Hsiang Fang
Yen-Hsiang Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150108508Abstract: A display panel comprising a substrate, a meshed shielding pattern, a plurality of light-emitting devices and a solar cell is provided. The substrate has a first surface and a second surface opposite to the first surface, the substrate comprises a first circuit layer disposed over the first surface and a second circuit layer disposed over the second surface. The meshed shielding pattern is disposed on first surface of the substrate to define a plurality of pixel regions over the substrate. The light-emitting devices are disposed on the first surface of the substrate and electrically connected to the first circuit layer, and at least one of the light-emitting devices is disposed in one of the pixel regions. The solar cell is disposed on the second surface of the substrate and electrically connected to the second circuit layer.Type: ApplicationFiled: December 30, 2014Publication date: April 23, 2015Inventors: Ming-Hsien Wu, Chia-Hsin Chao, Yen-Hsiang Fang, Yi-Chen Lin, Ying-Chien Chu, Mu-Tao Chu
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Publication number: 20150063386Abstract: A semiconductor laser structure is provided. The semiconductor laser comprises a central thermal shunt, a ring shaped silicon waveguide, a contiguous thermal shunt, an adhesive layer and a laser element. The central thermal shunt is located on a SOI substrate which has a buried oxide layer surrounding the central thermal shunt. The ring shaped silicon waveguide is located on the buried oxide layer and surrounds the central thermal shunt. The ring shaped silicon waveguide includes a P-N junction of a p-type material portion, an n-type material portion and a depletion region there between. The contiguous thermal shunt covers a portion of the buried oxide layer and surrounds the ring shaped silicon waveguide. The adhesive layer covers the ring shaped silicon waveguide and the buried oxide layer. The laser element covers the central thermal shunt, the adhesive layer and the contiguous thermal shunt.Type: ApplicationFiled: August 29, 2014Publication date: March 5, 2015Inventors: Jui-Ying Lin, Yen-Hsiang Fang, Chia-Hsin Chao, Yao-Jun Tsai, Yi-Chen Lin
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Patent number: 8946775Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0<tilted?0.5° with respect to a axis perpendicular to a (111) crystal plane, and the AlN layer is formed on the surface. The AlGaN layer is formed on the AlN layer. Moreover, an Al content in the AlGaN layer is decreased gradually in a layer thickness direction from the silicon substrate side toward the GaN layer side.Type: GrantFiled: August 22, 2012Date of Patent: February 3, 2015Assignee: Industrial Technology Research InstituteInventors: Chen-Zi Liao, Chih-Wei Hu, Yen-Hsiang Fang, Rong Xuan
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Patent number: 8779468Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.Type: GrantFiled: December 26, 2012Date of Patent: July 15, 2014Assignee: Industrial Technology Research InstituteInventors: Yen-Hsiang Fang, Chien-Pin Lu, Chen-Zi Liao, Rong Xuan, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
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Publication number: 20140124833Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.Type: ApplicationFiled: December 26, 2012Publication date: May 8, 2014Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yen-Hsiang Fang, Chien-Pin Lu, Chen-Zi Liao, Rong Xuan, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
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Publication number: 20140103354Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate includes a cubic silicon carbon nitride (SiCN) layer. The buffer layer is disposed on the nucleation layer. The nitride semiconductor layer is disposed on the buffer layer.Type: ApplicationFiled: October 9, 2013Publication date: April 17, 2014Applicant: Industrial Technology Research InstituteInventors: Chih-Wei Hu, Chen-Zi Liao, Yen-Hsiang Fang, Rong Xuan
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Publication number: 20140097444Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor layer is disposed on the buffer layer. The first type nitride semiconductor layer is doped with a first type dopant, at least one of the buffer layer and the first type nitride semiconductor layer comprises a codopant distributed therein, and an atomic radius of the codopant is larger than an atomic radius of the first type dopant. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer, the second type nitride semiconductor layer comprising a second type dopant.Type: ApplicationFiled: October 9, 2012Publication date: April 10, 2014Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yen-Hsiang Fang, Chen-Zi Liao, Rong Xuan, Chien-Pin Lu, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
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Publication number: 20140097443Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor stacked layer, a light-emitting layer and a second type nitride semiconductor layer. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor stacked layer is disposed on the buffer layer. The first type nitride semiconductor stacked layer being a plurality of lattice mismatch stacked layers includes a plurality of first nitride semiconductor layers and a plurality of second nitride semiconductor layers. The first nitride semiconductor layers and the second nitride semiconductor layers are stacked alternately, and the first nitride semiconductor layers and the second nitride semiconductor layers are different material. The light-emitting layer is disposed on the first type nitride semiconductor stacked layer.Type: ApplicationFiled: October 9, 2012Publication date: April 10, 2014Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yen-Hsiang Fang, Rong Xuan, Chen-Zi Liao, Yi-Keng Fu, Chih-Wei Hu, Chien-Pin Lu, Hsun-Chih Liu
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Publication number: 20140097442Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a first buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The first buffer layer is disposed on the nucleation layer. The first buffer layer includes a dopant and Gallium, and an atomic radius of the dopant is larger than an atomic radius of Gallium. The first type nitride semiconductor layer is disposed over the first buffer layer. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer.Type: ApplicationFiled: October 9, 2012Publication date: April 10, 2014Applicant: Industrial Technology Research InstituteInventors: Yen-Hsiang Fang, Chen-Zi Liao, Rong Xuan, Chien-Pin Lu, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
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Patent number: 8674393Abstract: A substrate structure is described, including a starting substrate, crystal piers on the starting substrate, and a mask layer. The mask layer covers an upper portion of the sidewall of each crystal pier, is connected between the crystal piers at its bottom, and is separated from the starting substrate by an empty space between the crystal piers. An epitaxial substrate structure is also described, which can be formed by growing an epitaxial layer over the above substrate structure form the crystal piers. The crystal piers may be broken after the epitaxial layer is grown.Type: GrantFiled: December 21, 2010Date of Patent: March 18, 2014Assignee: Industrial Technology Research InstituteInventors: Yih-Der Guo, Chu-Li Chao, Yen-Hsiang Fang, Ruey-Chyn Yeh, Kun-Fong Lin
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Publication number: 20140054593Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0<tilted?0.5° with respect to a axis perpendicular to a (111) crystal plane, and the AlN layer is formed on the surface. The AlGaN layer is formed on the AlN layer. Moreover, an Al content in the AlGaN layer is decreased gradually in a layer thickness direction from the silicon substrate side toward the GaN layer side.Type: ApplicationFiled: August 22, 2012Publication date: February 27, 2014Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chen-Zi Liao, Chih-Wei Hu, Yen-Hsiang Fang, Rong Xuan
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Patent number: 8604487Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes a base material, a patterned nitride semiconductor, a protection layer, and a nitride semiconductor layer. The patterned nitride semiconductor layer is located on the base material and includes a plurality of nanorod structures and a plurality of block patterns, and an upper surface of the nanorod structures is substantially coplanar with an upper surface of the block patterns. The protection layer covers a side wall of the nanorod structure sand a side wall of the block patterns. The nitride semiconductor layer is located on the patterned nitride semiconductor layer, and a plurality of nanopores are located between the nitride semiconductor layer and the patterned nitride semiconductor layer.Type: GrantFiled: December 19, 2011Date of Patent: December 10, 2013Assignee: Industrial Technology Research InstituteInventors: Yen-Hsiang Fang, Chu-Li Chao, Chih-Wei Hu, Yih-Der Guo
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Patent number: 8604488Abstract: A light emitting diode including a GaN substrate, a first type semiconductor layer, a light emitting layer, a second type semiconductor layer, a first electrode, and a second electrode is provided. The GaN substrate has a first surface and a second surface opposite thereto, and the second surface has a plurality of protuberances, the height of the protuberance is h ?m and the distribution density of the protuberance on the second surface is d cm?2, wherein 9.87×107?h2d, and h?1.8. The first type semiconductor is disposed on the first surface of the GaN substrate. The light emitting layer is disposed on a partial region of the first semiconductor layer, and the wavelength of the light emitted by the light emitting layer is from 375 nm to 415 nm. The second semiconductor layer is disposed on the light emitting layer.Type: GrantFiled: February 2, 2012Date of Patent: December 10, 2013Assignee: Industrial Technology Research InstituteInventors: Yi-Keng Fu, Ren-Hao Jiang, Yen-Hsiang Fang, Bo-Chun Chen, Chia-Feng Lin
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Patent number: 8482103Abstract: A nitride semiconductor template including a substrate, a mask layer, a first nitride semiconductor layer and a second nitride semiconductor is provided. The substrate has a plurality of trenches, each of the trenches has a bottom surface, a first inclined sidewall and a second inclined sidewall. The mask layer covers the second inclined sidewall and exposes the first inclined sidewall. The first nitride semiconductor layer is disposed over the substrate and the mask layer. The first nitride semiconductor layer fills the trenches and in contact with the first inclined sidewall. The first nitride semiconductor layer has voids located outside the trenches and parts of the mask layer are exposed by the voids. The first nitride semiconductor layer has a plurality of nano-rods. The second nitride semiconductor layer covers the nano-rods. The spaces between the nano-rods are not entirely filled by the second nitride semiconductor layer.Type: GrantFiled: December 9, 2010Date of Patent: July 9, 2013Assignee: Industrial Technology Research InstituteInventors: Hsun-Chih Liu, Chen-Zi Liao, Yen-Hsiang Fang, Rong Xuan, Chu-Li Chao
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Publication number: 20130112987Abstract: A light emitting diode including a GaN substrate, a first type semiconductor layer, a light emitting layer, a second type semiconductor layer, a first electrode, and a second electrode is provided. The GaN substrate has a first surface and a second surface opposite thereto, and the second surface has a plurality of protuberances, the height of the protuberance is h ?m and the distribution density of the protuberance on the second surface is d cm?2, wherein 9.87×107?h2d, and h?1.8. The first type semiconductor is disposed on the first surface of the GaN substrate. The light emitting layer is disposed on a partial region of the first semiconductor layer, and the wavelength of the light emitted by the light emitting layer is from 375 nm to 415 nm. The second semiconductor layer is disposed on the light emitting layer.Type: ApplicationFiled: February 2, 2012Publication date: May 9, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yi-Keng Fu, Ren-Hao Jiang, Yen-Hsiang Fang, Bo-Chun Chen, Chia-Feng Lin
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Publication number: 20120161148Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes a base material, a patterned nitride semiconductor, a protection layer, and a nitride semiconductor layer. The patterned nitride semiconductor layer is located on the base material and includes a plurality of nanorod structures and a plurality of block patterns, and an upper surface of the nanorod structures is substantially coplanar with an upper surface of the block patterns. The protection layer covers a side wall of the nanorod structure sand a side wall of the block patterns. The nitride semiconductor layer is located on the patterned nitride semiconductor layer, and a plurality of nanopores are located between the nitride semiconductor layer and the patterned nitride semiconductor layer.Type: ApplicationFiled: December 19, 2011Publication date: June 28, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yen-Hsiang Fang, Chu-Li Chao, Chih-Wei Hu, Yih-Der Guo
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Publication number: 20120153338Abstract: A substrate structure is described, including a starting substrate, crystal piers on the starting substrate, and a mask layer. The mask layer covers an upper portion of the sidewall of each crystal pier, is connected between the crystal piers at its bottom, and is separated from the starting substrate by an empty space between the crystal piers. An epitaxial substrate structure is also described, which can be formed by growing an epitaxial layer over the above substrate structure form the crystal piers. The crystal piers may be broken after the epitaxial layer is grown.Type: ApplicationFiled: December 21, 2010Publication date: June 21, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yih-Der Guo, Chu-Li Chao, Yen-Hsiang Fang, Ruey-Chyn Yeh, Kun-Fong Lin
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Publication number: 20120146190Abstract: A nitride semiconductor template including a substrate, a mask layer, a first nitride semiconductor layer and a second nitride semiconductor is provided. The substrate has a plurality of trenches, each of the trenches has a bottom surface, a first inclined sidewall and a second inclined sidewall. The mask layer covers the second inclined sidewall and exposes the first inclined sidewall. The first nitride semiconductor layer is disposed over the substrate and the mask layer. The first nitride semiconductor layer fills the trenches and in contact with the first inclined sidewall. The first nitride semiconductor layer has voids located outside the trenches and parts of the mask layer are exposed by the voids. The first nitride semiconductor layer has a plurality of nano-rods. The second nitride semiconductor layer covers the nano-rods. The spaces between the nano-rods are not entirely filled by the second nitride semiconductor layer.Type: ApplicationFiled: December 9, 2010Publication date: June 14, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hsun-Chih Liu, Chen-Zi Liao, Yen-Hsiang Fang, Rong Xuan, Chu-Li Chao
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Patent number: 7838135Abstract: A novel heat assisted magnetic recording (HAMR) medium and the fabrication method therefor are provided. The exchange coupling effect occurring at the interface of FePt/CoTb double layers is adopted, and thus the resulting magnetic flux would be sufficient enough to be detected and readout under the room temperature. The provided HAMR medium exhibits a relatively high saturation magnetization and perpendicular coercivity, and thus possesses a great potential for the ultra-high density recording application.Type: GrantFiled: August 4, 2006Date of Patent: November 23, 2010Inventors: Po-Cheng Kuo, Yen-Hsiang Fang, An-Cheng Sun, Tao-Hsuan Yang, Chun-Yuan Chou, Ching-Ray Chang
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Publication number: 20090246362Abstract: A novel heat assisted magnetic recording (HAMR) medium and the fabrication method therefor are provided. The exchange coupling effect occurring at the interface of FePt/CoTb double layers is adopted, and thus the resulting magnetic flux would be sufficient enough to be detected and readout under the room temperature. The provided HAMR medium exhibits a relatively high saturation magnetization and perpendicular coercivity, and thus possesses a great potential for the ultra-high density recording application.Type: ApplicationFiled: June 9, 2009Publication date: October 1, 2009Inventors: Po-Cheng Kuo, Yen-Hsiang Fang, An-Cheng Sun, Tao-Hsuan Yang, Chun-Yuan Chou, Ching-Ray Chang