Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.

Abstract: A static random access memory includes a first and second memory cell array, a first word line, a bit line, a bit line bar, a primary driver circuit, and a first and second supplementary driver circuit. The first supplementary driver circuit is configured to pull a voltage of a first signal of the bit line or a second signal of the bit line bar to a first voltage level during a write operation in response to a supplementary driver circuit enable signal. The second supplementary driver circuit is configured to sense the voltage of the first or second signal. The second supplementary driver circuit includes a first pass-gate transistor. A first terminal of the first pass-gate transistor is coupled to a reference voltage supply. A second terminal of the first pass-gate transistor is electrically floating. A third terminal of the first pass-gate transistor is coupled to a first node.

Abstract: A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, an output node, first and second switching devices coupled in series between the output node and the power supply node, and a third switching device directly coupled to each of the output node and the reference node. The first switching device is configured to selectively couple the output node to the second switching device responsive to a first data signal, the second switching device is configured to selectively couple the first switching device to the power supply node responsive to a second data signal, and the third switching device is configured to selectively couple the output node to the reference node responsive to the first data signal.

Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells that are connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver and local write drivers included correspondingly in the segments; and the global write driver including a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line, and the global write driver and the local write drivers each including first inversion couplings (coupled in parallel between the GWB line and the LWB line) and second inversion couplings (coupled in parallel between the GWB_bar line and the LWB_bar line).

Abstract: A device is disclosed that includes a fin structure disposed below a first metal layer, extending along a column direction, and corresponding to at least one transistor of a memory bit cell, a word line disposed in the first metal layer and extending along a row direction, a first metal island disposed in the first metal layer separated from the word line, and a first connection metal line disposed in a second metal layer above the first metal layer, extending along the column direction, and configured to couple a power supply through the first metal island to the fin structure. In a layout view, the first connection metal line is separated from the fin structure, and the fin structure crosses over the word line and the first metal island. A method is also disclosed herein.

Abstract: Systems and method are provided for a memory circuit. In embodiments, the circuit includes a plurality of memory cells corresponding to a word of data and a global write word line. A plurality of local write lines are connected to a subset of the plurality of memory cells of the word of data. Selection logic is configured to activate a particular subset of memory cells for writing via a particular local write line based on a signal on the global write word line and a selection signal associated with the particular subset of memory cells.

Abstract: A semiconductor chip is provided. The semiconductor chip includes a SRAM cell, a logic cell, a signal line and a ground line. The SRAM cell includes a storage transmission gate, a read transmission gate and a latch circuit. The latch circuit is serially connected between the storage and read transmission gates, and includes a first inverter, a second inverter and a transmission gate connected to an output of the first inverter, an input of the second inverter and an output of the storage transmission gate. The logic cell disposed aside the SRAM cell is connected with the SRAM cell by first and second active structures. The signal and ground lines extend at opposite sides of the SRAM and logic cells, and are substantially parallel with the first and second active structures. The SRAM and logic cells are disposed between and electrically connected to the signal and ground lines.

Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull down transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact. The first metal contact layout pattern overlaps the cell boundary of the memory circuit and the first active region layout pattern. The first metal contact electrically coupled to a source of the first pull down transistor. The memory circuit being a four transistor (4T) memory cell including a first and second pass gate transistor, and a first and second pull down transistor.

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Abstract: An SRAM includes multiple memory cells, each memory cell includes a data storage unit; a data I/O control adapted to input data to, and output data from, a data line; and multiple access controls respectively connected to at least two access control lines (WL's) and adapted to enable and disable the data input and output from the at least two WL's. The access controls are configured to permit data input only when both WL's are in their respective states that permit data input. A method of writing to a group of SRAM cells include sending a first write-enable signal to the cells via a first WL, sending a group of respective second write-enable signals to the respective cells, and, for each of the cells, preventing writing data to the cell if either of the first write-enable signal and respective second write enable signal is in a disable-state.

Abstract: An integrated circuit read only memory (ROM) structure includes a first ROM transistor with a first gate electrode, a first source, and a first drain, and a second ROM transistor with a second gate electrode, a second source, and a second drain. A drain conductive line is over the first drain and the second drain, and is between the first drain and the second drain. The first drain, the drain conductive line and the second drain are between the first gate electrode and the second gate electrode, and a first trench isolation structure electrically isolates the first drain from the first source is below the first gate electrode.

Abstract: Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.

Abstract: A charge sharing scheme is used to mitigate the variations in cell currents in order to achieve higher accuracy for CIM computing. In some embodiments, a capacitor is associated with each SRAM cell, and the capacitors associated with all SRAM cells in a column are included in averaging the RBL current. In some embodiments, a memory unit associated to an RBL in a CIM device includes a storage element adapted to store a weight, a first switch device connected to the storage element and adapted to be controlled by an input signal and generate a product signal having a magnitude indicative of the product of the input signal and the stored weight. The memory unit further includes a capacitor adapted to receive the product signal and store an amount of charge corresponding to the magnitude of the product signal. The memory unit further include a second switch device adapted to transfer the charge on the capacitor to the RBL.

Abstract: A memory device includes a conductive segment, first and second rows of memory cells. The conductive segment receives a first reference voltage signal. The first row of memory cells is coupled to a first word line. The second row of memory cells is coupled to a second word line. The first row of memory cells includes first and second memory cells. The first memory cell is coupled to the conductive segment to receive the first reference voltage signal. The second row of memory cells includes third and fourth memory cells. The third memory cell is coupled to the conductive segment to receive the first reference voltage signal. The first and third memory cells share the conductive segment, and the third memory cell is arranged between the first and second memory cells. The second memory cell is arranged between the third and fourth memory cells.

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

Abstract: Systems and method are provided for a memory circuit. In embodiments, the circuit includes a plurality of memory cells corresponding to a word of data and a global write word line. A plurality of local write lines are connected to a subset of the plurality of memory cells of the word of data. Selection logic is configured to activate a particular subset of memory cells for writing via a particular local write line based on a signal on the global write word line and a selection signal associated with the particular subset of memory cells.

Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.

Abstract: A static random access memory (SRAM) includes a first memory cell array, a second memory cell array, a first data line coupled to the first memory cell array and the second memory cell array, a second data line coupled to the first memory cell array and the second memory cell array, a primary driver circuit coupled to at least the first data line, and a supplementary driver circuit coupled to at least the first data line. The supplementary driver circuit is configured to receive a supplementary driver circuit enable signal, sense a voltage of a first signal of the first data line, and pull the voltage of the first signal to a first voltage level during a write operation of a first memory cell in the first memory cell array in response to at least a first NOR output signal.