Patents by Inventor Yen-Huei Chen

Yen-Huei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8928113
    Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Yu Pan, Jung-Hsuan Chen, Shao-Yu Chou, Yen-Huei Chen, Hung-Jen Liao
  • Publication number: 20140269024
    Abstract: A method of writing a memory cell includes, during a write cycle, causing a voltage level at a power terminal of the memory cell to change from a supply voltage level toward a first voltage level. The voltage level at the power terminal of the memory cell is maintained at the first voltage level for a first predetermined duration. The voltage level at the power terminal of the memory cell is maintained at a second voltage level for a second predetermined duration, where the second voltage level is between the first voltage level and the supply voltage level. During the write cycle, the voltage level at the power terminal of the memory cell is caused to change from the first voltage level toward the supply voltage level.
    Type: Application
    Filed: May 30, 2014
    Publication date: September 18, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Huei CHEN, Li-Wen WANG, Chih-Yu LIN
  • Publication number: 20140211578
    Abstract: One or more techniques or systems for boosting a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a RWL, a WWL, or a read write word line (RWWL). In some embodiments, the boosted word line signal includes a first stage and a second stage. For example, the first stage is associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level and the second stage is associated with a second stage voltage level above the Vdd voltage level. In this manner, a read or write operation is boosted for an SRAM bit cell, because the second stage boosts a corresponding transistor in the SRAM bit cell, for example.
    Type: Application
    Filed: January 30, 2013
    Publication date: July 31, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yen-Huei Chen, Chih-Yu Lin, Li-Wen Wang, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Publication number: 20140201692
    Abstract: Some embodiments relate to a system that pre-colors word lines and control lines within a memory cell to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The system has a memory element that stores a graphical IC layout with a memory circuit having layout features including a plurality of word lines and a plurality of Y-control lines. A pre-coloring element pre-colors one or more of the plurality of word lines and Y-control lines, to indicate that pre-colored word lines and Y-control lines are to be formed on a same mask of a multiple mask set used for a multiple patterning lithography process. A decomposition element assigns different colors to uncolored layout features of the memory circuit, to indicate that different colored memory features are to be formed on different masks of the multiple mask set.
    Type: Application
    Filed: March 18, 2014
    Publication date: July 17, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: YEN-HUEI CHEN, HUNG-JEN LIAO, JONATHAN TSUNG-YUNG CHANG
  • Patent number: 8773930
    Abstract: A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Kuei Lin, Hung-Jen Liao, Yen-Huei Chen, Fang Jao
  • Patent number: 8773923
    Abstract: A method for writing a memory cell in a specific write cycle is provided. The method includes the following steps: providing a first signal having a first transition edge in the specific write cycle; providing a second signal having a second transition edge in the specific write cycle, wherein the second transition edge lags behind the first transition edge; providing a first voltage level to the memory cell; and lowering the first voltage level to a second voltage level in the specific write cycle for writing the memory cell in response to the second transition edge. A memory device is also provided.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Huei Chen, Li-Wen Wang, Chih-Yu Lin
  • Publication number: 20140185363
    Abstract: Among other things, techniques for facilitating a write operation to a bit cell are provided. A pulse generator initializes lowering of an internal voltage level associated with a bit cell that is to be written to by a write operation. In this way, the bit cell is placed into a writeable voltage state, such that a potential of the bit cell can be overcome by the write operation. A voltage detector sends a reset signal to the pulse generator based upon the pulse generator lowering the internal voltage level past a reset trigger level. Responsive to receiving the reset signal, the pulse generator initializes charging of the internal voltage level to an original voltage level. In this way, the lowering of the internal voltage level is controlled so that one or more other bit cells are not affected (e.g., suffer data retention failure) by the relatively lower internal voltage level.
    Type: Application
    Filed: December 30, 2012
    Publication date: July 3, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei Min Chan, Yi-Tzu Chen, Wei-Cheng Wu, Yen-Huei Chen, Hau-Tai Shieh
  • Patent number: 8767493
    Abstract: An SRAM differential voltage sensing apparatus is coupled to a memory circuit. The memory circuit comprises a memory bank, a plurality of bit lines, a plurality of data lines coupled to the plurality of bit lines via a plurality of transmission gates and a sense amplifier. When the sense amplifier operates in a characterization mode, the transmission gates and pre-charge circuits are turned off. The differential voltage sensing apparatus applies a characterization signal to the sense amplifier and obtains the parameters of the memory circuit through a trial and error process.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Huei Chen, Kun-hsi Li, Shao-Yu Chou, Hung-Jen Liao, Wei Min Chan
  • Publication number: 20140133219
    Abstract: Some embodiments of the present disclosure relate to a memory array having a cell voltage generator configured to provide a cell voltage header to a plurality of memory cells. The cell voltage generator is connected to the memory cells by way of supply voltage line and controls a supply voltage of the memory cells. The cell voltage generator has a pull-down element coupled between a control node of the supply voltage line and a ground terminal, and a one or more pull-up elements connected in parallel between the control node and a cell voltage source. A control unit is configured to provide one or more variable valued pull-up enable signals to input nodes of the pull-up elements. The variable valued pull-up enable signals operate the pull-up elements to selectively connect the supply voltage line from the cell voltage source to provide a cell voltage header with a high slew rate.
    Type: Application
    Filed: November 12, 2012
    Publication date: May 15, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Wei-Cheng Wu, Wei Min Chan, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 8723265
    Abstract: A multiple finger structure comprises a plurality of active regions placed between a pair of dummy POLY lines. The active regions comprise a plurality of multiple fingered NMOS transistors, which are part of a sense amplifier of an SRAM memory circuit. The drain and source of each multiple fingered NMOS transistor have an SiP/SiC epitaxial growth region. The active regions extend and overlap with the dummy POLY lines. The overlap between the active regions and the dummy POLY lines helps to reduce edge imperfection at the edge of the active regions.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: May 13, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Huei Chen, Wei Min Chan, Shao-Yu Chou, Hung-Jen Liao
  • Publication number: 20140119101
    Abstract: Some aspects of the present disclosure a method. In this method, a wordline voltage is provided to a wordline, which is coupled to a plurality of memory cells. A boost enable signal is provided. The state of the boost enable signal is indicative of whether the wordline voltage at a predetermined position on the wordline has reached a non-zero, predetermined wordline voltage. The wordline voltage is selectively boosted to a boosted wordline voltage level based on the boost enable signal.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Li-Wen Wang, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 8713491
    Abstract: Some embodiments relate to a method of pre-coloring word lines and control lines within an SRAM integrated chip design to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The method is performed by generating a graphical IC layout file having an SRAM circuit with a plurality of word lines and Y-control lines. The word lines and Y-control lines are assigned a color during decomposition. The word lines and Y-control lines are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. Therefore, during mask building, data associated with pre-colored word and Y-control lines is sent to a same mask, regardless of the colors that are assigned to the data. By assigning word and Y-control lines to a same mask through pre-coloring, processing variations between the word and Y-control lines are minimized, thereby mitigating timing variations in an SRAM circuit.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 8693265
    Abstract: A semiconductor memory includes first and second memory storage latches each including first and second ports. A first pair of bit lines is coupled to the first ports, and a second pair of bit lines is coupled to the second ports. The first and second pairs of bit lines are twisted between the first and second memory storage latches. A first sense amplifier is coupled to the first pair of bit lines for outputting data, and a second sense amplifier is coupled to the second pair of bit lines for outputting an intermediate data signal. Output logic circuitry is coupled to an output of the second sense amplifier and is configured to output data based on the intermediate data signal and a control signal that identifies if the data is being read from the first memory storage latch or from the second memory storage latch.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Kuei Lin, Jonathan Tsung-Yung Chang, Hung-Jen Liao, Yen-Huei Chen, Jhon Jhy Liaw
  • Patent number: 8692333
    Abstract: A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Huei Chen, You-Cheng Xiao, Jung-Hsuan Chen, Shao-Yu Chou
  • Publication number: 20140073124
    Abstract: A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate.
    Type: Application
    Filed: November 14, 2013
    Publication date: March 13, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Huei CHEN, Jung-Hsuan CHEN, Shao-Yu CHOU, Hung-Jen LIAO, Li-Chun TIEN
  • Patent number: 8670637
    Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Cheng Chang, Jin-Lien Lin, Kuo-Ching Hsu, Kai-Ming Ching, Jiun Yi Wu, Yen-Huei Chen
  • Publication number: 20140068531
    Abstract: Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes. The IC shapes within the graphical IC layout file are assigned a color during decomposition. The IC shapes are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. During mask building data associated with IC shapes that have been pre-colored is automatically sent to a same mask, regardless of the colors that are assigned to the shapes. Therefore, the pre-colored shapes are not assigned to a masked based upon a decomposition, but rather based upon the pre-coloring. By assigning IC shapes to a same mask through pre-coloring, overlay errors can be reduced.
    Type: Application
    Filed: November 11, 2013
    Publication date: March 6, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Huei Chen, Wei Min Chan, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 8665658
    Abstract: A semiconductor memory includes a memory array having at least one bit line, a tracking bit line, and a global tracking circuit. The tracking bit line is configured to emulate a voltage transition of the at least one bit line. The global tracking circuit is configured to generate a timing signal for generating a negative voltage with respect to ground on the at least one bit line of the memory array.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yen-Huei Chen
  • Patent number: 8644087
    Abstract: A circuit includes a first circuit configured to sense a leakage of a first bit line and output a first signal in response, and a second circuit configured to receive the first signal output from the first circuit and in response supply current to a second bit line for maintaining a voltage level of the second bit line.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: February 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jihi-Yu Lin, Li-Wen Wang, Wei Min Chan, Yen-Huei Chen
  • Publication number: 20140029358
    Abstract: A method for writing a memory cell in a specific write cycle is provided. The method includes the following steps: providing a first signal having a first transition edge in the specific write cycle; providing a second signal having a second transition edge in the specific write cycle, wherein the second transition edge lags behind the first transition edge; providing a first voltage level to the memory cell; and lowering the first voltage level to a second voltage level in the specific write cycle for writing the memory cell in response to the second transition edge. A memory device is also provided.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Huei CHEN, Li-Wen WANG, Chih-Yu LIN